中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.019 seconds)

    24.
    发明专利
    未知

    公开(公告)号：DE2237944A1

    公开(公告)日：1973-02-15

    申请号：DE2237944

    申请日：1972-08-02

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G06F3/06 ,  G11B20/10

    Abstract: Improved peripheral I/O devices, such as magnetic tape units and I/O controllers, are provided by selectively gating operational state indicating signals over multiplexed lines to an I/O controlling unit for continuously indicating intermediate operational states. The I/O controller, which may be a microprogrammed controller, responds to the intermediate state indications for monitoring and ensuring the intermediate operational states are properly maintained. Upon termination of the intermediate operational state, the next status of the I/O device is sensed. Supplying intermediate operational state conditions enables the I/O controller to sense when malfunctions have occurred which prevent the device from informing the I/O controller that such malfunctions have, in fact, occurred.

    26.
    发明专利
    未知

    公开(公告)号：DE3852695T2

    公开(公告)日：1995-06-29

    申请号：DE3852695

    申请日：1988-10-03

    Applicant: IBM

    Inventor： FOGG RICHARD GREGORY ,  IRWIN JOHN WILLIAM

    IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  G06F15/16 ,  G09G1/16

    Abstract: A multi-processor system includes at lteast a main processor, a co-processor and a video buffer store coupled to accept data from either of the processors for display. In order to maintain a record of data for display from the co-processor when the main processor is controlling the video buffer, a shadow video buffer is provided. This maintains an updated version of display data from the co-processor at all times. When the main processor is controlling the video buffer, the co-processor accesses the shadow buffer. When the co-processor is controlling the video buffer, it updates both the video buffer and the shadow buffer simultaneously.

    PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES
    27.
    发明专利
    PLURAL PROCESSOR SYSTEMS HAVING SHARED RESOURCES 未知

    公开(公告)号：HK19190A

    公开(公告)日：1990-03-23

    申请号：HK19190

    申请日：1990-03-15

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G06F13/24 ,  G06F13/26 ,  G06F13/28 ,  G06K9/00 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F9/46

    Abstract: Data processing system including a main processor (11) and a co-processor (22) sharing the same I/O facilities (17,18,19) as the main processor (11) and running software unknown to the main processor (11). The main processor (11) can concurrently run other software and maintains priority over shared I/O facilities (17,18,19) by providing trapping logic incorporated in a random access memory and dynamically loadable by the main processor (11) which contains data related to the current useability by the co-processor (22) of a shared I/O device (17). Additional logic is associated with the co-processor (22) to manage interrupts between the co-processor (22) and the system bus (16).

    29.
    发明专利
    未知

    公开(公告)号：DE2259236A1

    公开(公告)日：1973-06-28

    申请号：DE2259236

    申请日：1972-12-04

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G06F3/06 ,  G11B20/12 ,  G11B5/02

    Abstract: Digital magnetic records on a magnetic tape are formed independent of velocity deviations from a nominal or design velocity. A given length of media is designated for each record to be recorded. Such length is established to more than accommodate signals to be recorded by a predetermined maximum velocity of transport. Upon completing recording a given block of signals, a padding area is established until a given length of media has been relatively displaced with respect to a transducer regardless of the velocity during recording

    IMPROVEMENTS IN MAGNETIC RECORDING AND REPRODUCING SYSTEMS
    30.
    发明专利
    IMPROVEMENTS IN MAGNETIC RECORDING AND REPRODUCING SYSTEMS 未知

    公开(公告)号：GB1287220A

    公开(公告)日：1972-08-31

    申请号：GB5990370

    申请日：1970-12-17

    Applicant: IBM

    Inventor： IRWIN JOHN WILLIAM

    IPC: G11B20/14 ,  G11B20/20

    Abstract: 1287220 Magnetic data stores INTERNATIONAL BUSINESS MACHINES CORP 17 Dec 1970 [29 Dec 1969] 59903/70 Heading G4C In a parallel-bit magnetic recording system groups of data signals alternate with groups of synchronizing signals along each track. In the event of dead-tracking (i.e. if any read head is not providing error-free data, e.g. due to tape lift-off) the sync. group subsequently read from the dead track is used to resynchronize the signals read from all the tracks. As described each block of signals, Fig. 1, comprises a preamble 10 and postamble 24 bounding alternate data groups 12, 16, 22a and sync. groups 14, 20. Each data group is preceded by start marker bits 0.1 (11, 15, 21) and followed by end marker bits 1.0(13, 17,23). The number of bits between the beginning of successive groups is constant. As the final data group 22a may not contain as many bits as do earlier groups padding bits P are added to make the number of bits in the group marked 22 divisible by the capacity (e.g. 16) of a counter associated with the read/write circuitry. The bits are recorded in self-clocking form, a byte being recorded in parallel tracks and including a parity bit. The tape may be read in either direction of motion. Write mode, Figs. 3A, 3B (not shown).-When a data byte is present in the input/output register the tape motion is started. A predetermined number (e.g. 28) of preamble sync. bits 10 are recorded, followed by a first marker 11. The byte is then recorded and a byte counter, set to the number of bytes in a data group (e.g. 1024), is decremented by one. Further bytes are recorded until the data group is complete. The byte counter now being at zero a sync. group preceded by end marker bits is recorded under the control of a sync. bit counter. If now there are further bytes available the byte counter is reset (to 1024) and the recording of a further data group occurs. Should there be no further bytes available when the byte counter has not reached zero, padding bits are added, preceded by end marker bits. Postamble sync. bits are now recorded under the control of the sync. bit counter. Read mode, Fig. 4, 5 (not shown).-After reading the preamble bits 10 and the marker bits 11, data bytes are transferred to the output register via deskewing circuitry and error detection/correction circuitry. As each byte is transferred the count in the byte counter is stepped. When the counter indicates that the complete byte has been read, or when an end marker is detected prior to this (e.g. marker 23 following short data group 22a) a sync. cycle takes place as described below. If the tape is moving backwards it is necessary to ignore the padding signals P. This is done by sensing the end marker 23 and by altering the byte counter by the number of padding bits read. Data group 22a is then read and the byte counter adjusted at each byte transfer as described above. If the tape is moving forward and the check bit which immediately follows each data group has been transferred to the output register the byte counter should be at a preset count. If it is not reading is stopped, but if it is at this count, or if the tape is moving backwards, reading continues until the counter reaches a second preset count at which each of the read head should be reading a sync. group. At this point a check is made to determine whether any track which had been dead is by now resynchronized, and then the dead track is requeued in the skew buffers by placing the dead track at the maximum leading position relative to the most lagging active track. Provided that at least a preset number of tracks are giving satisfactory signals a test is made to determine that the maximum skew in the tracks does not exceed the correction capability of the circuitry. If a byte has been assembled in the skew circuitry successful readout of the dead track has been achieved and reading of the next data group proceeds as before.

Patent Agency Ranking