公开(公告)号：FR2385147A1

公开(公告)日：1978-10-20

申请号：FR7804190

申请日：1978-02-08

Applicant: IBM

Inventor： GANNON PATRICK M ,  HELLER ANDREW R ,  SMITH RONALD M ,  SITE RICHARD L

IPC: G06F12/10 ,  G06F12/1036 ,  G06F9/20

Abstract: Special controls in a processor prevent synonym entries in a translation look aside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses. The controls use a synonym resolution register (SRR) which divides each address space in the system into common and private portions. Fields in the SRR indicate which portions are to be common to all address spaces, and which portions are private in each address space. A SRR control circuit selects a particular status field under control of a virtual address requesting main storage access.

公开(公告)号：CA733662A

公开(公告)日：1966-05-03

申请号：CA733662D

Applicant: IBM

Inventor： VEER JOHN A DE ,  CASE RICHARD P ,  SMITH RONALD M ,  JONES HENRY G