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    SELF-ALIGNED METHOD FOR MAKING BIPOLAR TRANSISTOR HAVING MINIMUM BASE TO EMITTER CONTACT SPACING
    27.
    发明专利
    SELF-ALIGNED METHOD FOR MAKING BIPOLAR TRANSISTOR HAVING MINIMUM BASE TO EMITTER CONTACT SPACING 未知

    公开(公告)号：CA1142275A

    公开(公告)日：1983-03-01

    申请号：CA365461

    申请日：1980-11-25

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/203

    Abstract: Self Aligned Method For Making Bipolar Transistor Having Minimum Base to Emitter Contact Spacing A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite Conductivity epitaxial layer and substrate. Multiple layered mesas of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

    HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME
    28.
    发明专利
    HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME 未知

    公开(公告)号：CA1097825A

    公开(公告)日：1981-03-17

    申请号：CA307631

    申请日：1978-07-18

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

    Abstract: HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulatinq layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

    30.
    发明专利
    未知

    公开(公告)号：IT1165311B

    公开(公告)日：1987-04-22

    申请号：IT2584979

    申请日：1979-09-20

    Applicant: IBM

    Inventor： KONIAN RICHARD R ,  WALSH JAMES L

    IPC: H03K17/60 ,  H03K17/66 ,  H03K19/086 ,  H03K

    Abstract: A high speed current switch logic circuit wherein a first and a second transistor are operated in a current switching mode and wherein a third and a fourth transistor are provided whereby the current switching operation of the first and second transistor causes current switching operation of the third and fourth transistors and push pull switching of power to a load.

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