公开(公告)号：US3614560A

公开(公告)日：1971-10-19

申请号：US3614560D

申请日：1969-12-30

Applicant: IBM

Inventor： ANANTHA NARASIPUR G

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/08 ,  H01L19/00

CPC classification number: H01L29/0821 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  Y10S148/142

Abstract: A semiconductor device comprising in combination: a first zone of semiconductive material containing impurity atoms of the acceptor type; a contiguous second zone of semiconductive material containing a predetermined low concentration of impurity atoms of the donor type; a metal layer having an interface with said second zone; and a third zone of relatively highly conductive semiconductive material in contact with said metal layer and containing a high concentration of impurity atoms of either the donor or acceptor type. In a typical device in accordance with this invention the ''''first zone'''' is formed as a P+ diffusion area in the ''''second zone'''' which is of the Nconductivity type of silicon, the ''''metal'''' is platinum, the ''''third zone'''' is formed by P+ diffusion into a monocrystalline silicon wafer, and emitter, base and collector leads are in contact with said first, second and third zones, respectively.

公开(公告)号：CA1051122A

公开(公告)日：1979-03-20

申请号：CA267943

申请日：1976-12-15

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  JAMBOTKAR CHAKRAPANI G ,  WANG PAUL P

IPC: H01L29/44

Abstract: POWER TRANSISTOR HAVING IMPROVED SECOND BREAKDOWN CAPABILITY A high voltage power transistor of the type that includes emitter, base and collector regions of alternate conductivity types and PN junctions at the interface of the emitter and base regions, and at the interface of the base and collector regions. The improvement being an emitter region having at least a plurality of spaced elongated finger-like portions; a means in the base region to lower the base resistance in the transverse direction, this means located centrally beneath the finger-like portions of the emitter and comprised either of regions of low resistivity located centrally and beneath each of the finger-like portions, or regions of increased base thickness in the vertical direction also located centrally beneath each of the finger-like portions of the emitter.

公开(公告)号：FR2373126A1

公开(公告)日：1978-06-30

申请号：FR7731856

申请日：1977-10-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  CHANG FUNG Y ,  RUBIN BARRY J

IPC: G11C27/04 ,  G11C11/56 ,  G11C19/28 ,  G11C19/36 ,  H03H11/26

公开(公告)号：CA934477A

公开(公告)日：1973-09-25

申请号：CA89298

申请日：1970-07-28

Applicant: IBM

Inventor： ASHAR KANU G ,  ANANTHA NARASIPUR G

IPC: H01L29/872 ,  H01L21/00 ,  H01L21/762 ,  H01L23/29 ,  H01L29/00 ,  H01L29/47

公开(公告)号：CA1142275A

公开(公告)日：1983-03-01

申请号：CA365461

申请日：1980-11-25

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/203

Abstract: Self Aligned Method For Making Bipolar Transistor Having Minimum Base to Emitter Contact Spacing A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite Conductivity epitaxial layer and substrate. Multiple layered mesas of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

公开(公告)号：CA1097825A

公开(公告)日：1981-03-17

申请号：CA307631

申请日：1978-07-18

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulatinq layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：DE2458847A1

公开(公告)日：1975-07-31

申请号：DE2458847

申请日：1974-12-12

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  DOCKERTY ROBERT C

IPC: H01L29/00 ,  H01L29/47 ,  H01L29/872 ,  H01L29/48

公开(公告)号：DE3485457D1

公开(公告)日：1992-02-27

申请号：DE3485457

申请日：1984-11-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  GAUR SANTOSH P ,  HUANG YI-SHIOU ,  TSANG PAUL J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8224 ,  H01L29/08 ,  H01L29/735 ,  H01L21/00 ,  H01L21/82

Abstract: A method for making a lateral PNP transistor (simultaneously with an NPN transistor) and the resultant device wherein a first mask (76) defines a base-width by the resistor implant (78, 80) for a P-type resistor and a second mask (86) is overlaid asymmetricially on said first mask to partially cover the collector (80). At the same time that the NPN extrinsic base contact is made, P-type dopants-are introduced in the areas (88, 89) exposed by the first and second masks to provide an emitter (92) and a collector contact (94) for the PNP transistor, said transistor thus featuring a graded collector (96, 94) with a high punch-through voltage.

公开(公告)号：CA1148274A

公开(公告)日：1983-06-14

申请号：CA368426

申请日：1981-01-13

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/329 ,  H01L29/47 ,  H01L29/872 ,  H01L21/465

Abstract: Method for Making Stable Nitride-Defined Schottky Barrier Diodes Excessive leakage after initial forward stress, exhibited by subsequently reverse stressed nitride defined, Schottky barrier diodes is solved by the elimination of the "mouse hole" or undercut cavity in the oxide layer beneath the nitride ring defining the Schottky contact to the underlying silicon. The aforementioned cavity is filled by depositing chemical vapor deposited (CVD) oxide onto the nitride layer, into the nitride ring and the undercut oxide cavity beneath the ring and onto the underlying silicon substrate exposed through the nitride ring. The CVD oxide is then reactively ion etched to remove it except along the vertical walls of the nitride ring and the oxide cavity. The Schottky metal is deposited on the silicon substrate exposed by the reactive ion etching step. FI 9-79-061

公开(公告)号：CA1102011A

公开(公告)日：1981-05-26

申请号：CA307633

申请日：1978-07-18

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  CHANG AUGUSTINE W

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/82 ,  H01L21/822 ,  H01L27/08 ,  H01L27/118 ,  H01L29/73 ,  H01L29/8605 ,  H01L29/861 ,  H01L21/86

Abstract: HIGH SHEET RESISTANCE STRUCTURE FOR HIGH DENSITY INTEGRATED CIRCUITS A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.