中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.019 seconds)

    METHOD FOR MAKING STABLE NITRIDE-DEFINED SCHOTTKY BARRIER DIODES
    2.
    发明专利
    METHOD FOR MAKING STABLE NITRIDE-DEFINED SCHOTTKY BARRIER DIODES 未知

    公开(公告)号：CA1148274A

    公开(公告)日：1983-06-14

    申请号：CA368426

    申请日：1981-01-13

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S

    IPC: H01L21/306 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/329 ,  H01L29/47 ,  H01L29/872 ,  H01L21/465

    Abstract: Method for Making Stable Nitride-Defined Schottky Barrier Diodes Excessive leakage after initial forward stress, exhibited by subsequently reverse stressed nitride defined, Schottky barrier diodes is solved by the elimination of the "mouse hole" or undercut cavity in the oxide layer beneath the nitride ring defining the Schottky contact to the underlying silicon. The aforementioned cavity is filled by depositing chemical vapor deposited (CVD) oxide onto the nitride layer, into the nitride ring and the undercut oxide cavity beneath the ring and onto the underlying silicon substrate exposed through the nitride ring. The CVD oxide is then reactively ion etched to remove it except along the vertical walls of the nitride ring and the oxide cavity. The Schottky metal is deposited on the silicon substrate exposed by the reactive ion etching step. FI 9-79-061

    SELF-ALIGNED METHOD FOR MAKING BIPOLAR TRANSISTOR HAVING MINIMUM BASE TO EMITTER CONTACT SPACING
    6.
    发明专利
    SELF-ALIGNED METHOD FOR MAKING BIPOLAR TRANSISTOR HAVING MINIMUM BASE TO EMITTER CONTACT SPACING 未知

    公开(公告)号：CA1142275A

    公开(公告)日：1983-03-01

    申请号：CA365461

    申请日：1980-11-25

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L23/532 ,  H01L21/203

    Abstract: Self Aligned Method For Making Bipolar Transistor Having Minimum Base to Emitter Contact Spacing A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite Conductivity epitaxial layer and substrate. Multiple layered mesas of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

    HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME
    7.
    发明专利
    HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME 未知

    公开(公告)号：CA1097825A

    公开(公告)日：1981-03-17

    申请号：CA307631

    申请日：1978-07-18

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR G ,  BHATIA HARSARAN S ,  WALSH JAMES L

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

    Abstract: HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulatinq layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

Patent Agency Ranking