公开(公告)号：DE60234900D1

公开(公告)日：2010-02-11

申请号：DE60234900

申请日：2002-11-13

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06T3/40

Abstract: An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a memory (28), such as a DRAM memory, that are serially connected. The input pattern (23) is applied to a processor (22), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (24). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern (25) using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.

公开(公告)号：AT453903T

公开(公告)日：2010-01-15

申请号：AT02368124

申请日：2002-11-13

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06T3/40

Abstract: An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a memory (28), such as a DRAM memory, that are serially connected. The input pattern (23) is applied to a processor (22), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (24). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern (25) using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.

公开(公告)号：AT364866T

公开(公告)日：2007-07-15

申请号：AT00480106

申请日：2000-11-14

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL ,  LOUIS DIDIER

IPC: G06F7/02 ,  G06F7/22 ,  G06F7/544

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

公开(公告)号：DE60206194D1

公开(公告)日：2005-10-20

申请号：DE60206194

申请日：2002-07-11

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

公开(公告)号：AT304725T

公开(公告)日：2005-09-15

申请号：AT02758409

申请日：2002-07-11

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

公开(公告)号：DE60035171T2

公开(公告)日：2008-02-14

申请号：DE60035171

申请日：2000-11-14

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL ,  LOUIS DIDIER

IPC: G06F7/02 ,  G06F7/22 ,  G06F7/544

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

公开(公告)号：DE60035171D1

公开(公告)日：2007-07-26

申请号：DE60035171

申请日：2000-11-14

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL ,  LOUIS DIDIER

IPC: G06F7/02 ,  G06F7/22 ,  G06F7/544

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

公开(公告)号：AU2002304860A1

公开(公告)日：2002-10-15

申请号：AU2002304860

申请日：2002-02-25

Applicant: IBM

Inventor： TANNHOF PASCAL

IPC: G06N3/063

公开(公告)号：DE68924426D1

公开(公告)日：1995-11-02

申请号：DE68924426

申请日：1989-10-26

Applicant: IBM

Inventor： MOLLIER PIERRE ,  NUEZ JEAN-PAUL ,  TANNHOF PASCAL

IPC: H03K19/013 ,  H03K19/086

Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

公开(公告)号：DE3854155D1

公开(公告)日：1995-08-17

申请号：DE3854155

申请日：1988-04-29

Applicant: IBM

Inventor： MOLLIER PIERRE ,  TANNHOF PASCAL

IPC: H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

Abstract: The present invention relates in general to fast logic circuits, and more particularly to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A typical 3 Way OR/NOR circuit includes a standard differential amplifier (DA), the first branch of which is controlled by logic input signals (E1, E3, E3). The second branch includes a current switch (T12) controlled by a reference voltage (VREF). The differential amplifier provides first and second output signals (S1, S2), simultaneous and complementary each other. The circuit further includes two push pull output buffers (PP21, PP22). First output buffer (PP21) comprises an active pull up device (FET T13) connected in series with an active pull down device (FET T20), the first circuit output signal (A1) is available at their common node or at the output terminal (21). The active pull up device (T13) is controlled by a first output signal (S1) of the differential amplifier, the active pull down device (T20) is preferably controlled by the second output signal (S2) through an intermediate source follower buffer (IB22). The second output buffer (PP22) is of similar structure, in order to supply the complementary second circuit output signal (B1). The circuit takes advantage of the fact that output signals (S1, S2) are available simultaneously and complementary each other on the outputs of the differential amplifier at output nodes (13, 14) to perform the logic function. The depicted circuit is of the dual phase type because it provides complementary circuit output signals (A1, B1). However, if only one phase of the circuit output signal (e.g. A1) is needed, the number of required devices can be reduced in the output circuit block (16). The output buffer (PP22) and the intermediate buffer (IB21) which cooperate to supply the opposite phase (B1) can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer (IB22). The gate electrode of the active pull down device (T20) is directly controlled by the second output signal (S2) complementary to the first output signal (S1) which controls the corresponding active pull up device (T13).