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    TRUE/COMPLEMENT GENERATOR
    1.
    发明专利
    TRUE/COMPLEMENT GENERATOR 未知

    公开(公告)号：DE3279782D1

    公开(公告)日：1989-07-27

    申请号：DE3279782

    申请日：1982-03-24

    Applicant: IBM ,  IBM FRANCE

    Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

    IPC: G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  G11C8/00

    Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value ( phi ), the second one providing the complement ( phi ) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of ( phi ) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output phi . Transistor T11-2 in the second circuit prevents phi from going high as long as it is maintained on by the level provided by R10-1, R11-2 from phi .

    4.
    发明专利
    未知

    公开(公告)号：DE68924426T2

    公开(公告)日：1996-05-02

    申请号：DE68924426

    申请日：1989-10-26

    Applicant: IBM

    Inventor： MOLLIER PIERRE ,  NUEZ JEAN-PAUL ,  TANNHOF PASCAL

    IPC: H03K19/013 ,  H03K19/086

    Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

    6.
    发明专利
    未知

    公开(公告)号：DE68924426D1

    公开(公告)日：1995-11-02

    申请号：DE68924426

    申请日：1989-10-26

    Applicant: IBM

    Inventor： MOLLIER PIERRE ,  NUEZ JEAN-PAUL ,  TANNHOF PASCAL

    IPC: H03K19/013 ,  H03K19/086

    Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

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