-
公开(公告)号：JP2001236207A
公开(公告)日：2001-08-31
申请号：JP2000387095
申请日：2000-12-20
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , LOUIS DIDIER , TANNHOF PASCAL
Abstract: PROBLEM TO BE SOLVED: To retrieves the minimum/maximum values in the group of numbers. SOLUTION: At first, p numbers encoded on q bits are turned into K (q>=K×n) partial values encoded on n bits, and parameters k (k=1-K) for respectively assigning ranks to the partial value of each number are defined so that K bit slices can be formed, and each slice is constituted of the plural partial values having the same rank. Then, each partial value is encoded on m bits (m>n) by using a 'thermometric' encoding technique. Afterwards, the minimum partial value in the first slice (MSB) of the encoded partial values is decided by a parallel type retrieval, and all the numbers related with the larger partial values than the partial value are selectively released. An evaluation process is repeated in the same configuration until the last slice (LSB) is processed, and the number selected as it is in the final stage is allowed to have the minimum value.
-
公开(公告)号：DE69430870T2
公开(公告)日：2003-03-13
申请号：DE69430870
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , GODEFROY CATHERINE , STEIMLE ANDRE , LOUIS DIDIER , PAILLET GUY , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and second intermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories. The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feed-back signal.
-
公开(公告)号：DE69430527T2
公开(公告)日：2003-01-02
申请号：DE69430527
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , PAILLET GUY , LOUIS DIDIER
Abstract: In a neural network comprised of a plurality of neuron circuits being either in an engaged or a free state, there is disclosed a pre-charge circuit placed in each neuron circuit that allows to load the components of an input vector (A) only in a determined free neuron circuit during the recognition phase as the components of the prototype vector (B) attached to this neuron circuit. The pre-charge circuit consists of a weight memory (251) controlled by a memory control signal (RS) and of a circuit generating said memory control signal which is adapted to identify the said determined free neuron circuit. During the recognition phase, the memory control signal is thus set active only for the said determined free neuron circuit. When the neural network is structured as a chain of neuron circuits, said determined free neuron circuit is the first free in the chain. The input data bus (DATA-BUS) transporting the input vector components is connected to the weight memory of all neuron circuits. The data outputted therefrom are available on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) to properly address the weight memory and a register (253) to latch the data that are outputted on the output data bus. After this neuron circuit has been engaged, the contents of its weight memory cannot be modified any longer. To perform the pre-charge of the input vector during the recognition phase makes the engagement process more efficient and significantly reduces the learning time of the input vector.
-
公开(公告)号：CA2149478A1
公开(公告)日：1996-01-29
申请号：CA2149478
申请日：1995-05-16
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , LOUIS DIDIER , GODEFROY CATHERINE , PAILLET GUY , STEIMLE ANDRE , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and secondintermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories . The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feedback signal.
-
Patent Agency Ranking
公开(公告)号：DE60035171T2
公开(公告)日：2008-02-14
申请号：DE60035171
申请日：2000-11-14
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL , LOUIS DIDIER
Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
-
公开(公告)号：DE60035171D1
公开(公告)日：2007-07-26
申请号：DE60035171
申请日：2000-11-14
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL , LOUIS DIDIER
Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
-
公开(公告)号：DE69430870D1
公开(公告)日：2002-08-01
申请号：DE69430870
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： BOULET JEAN YVES , GODEFROY CATHERINE , STEIMLE ANDRE , LOUIS DIDIER , PAILLET GUY , TANNHOF PASCAL
Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and second intermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories. The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feed-back signal.
-
公开(公告)号：AT364866T
公开(公告)日：2007-07-15
申请号：AT00480106
申请日：2000-11-14
Applicant: IBM
Inventor： IMBERT DE TREMIOLLES GHISLAIN , TANNHOF PASCAL , LOUIS DIDIER
Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.
-
公开(公告)号：DE69430527D1
公开(公告)日：2002-06-06
申请号：DE69430527
申请日：1994-07-28
Applicant: IBM , PAILLET GUY
Inventor： STEIMLE ANDRE , PAILLET GUY , LOUIS DIDIER
Abstract: In a neural network comprised of a plurality of neuron circuits being either in an engaged or a free state, there is disclosed a pre-charge circuit placed in each neuron circuit that allows to load the components of an input vector (A) only in a determined free neuron circuit during the recognition phase as the components of the prototype vector (B) attached to this neuron circuit. The pre-charge circuit consists of a weight memory (251) controlled by a memory control signal (RS) and of a circuit generating said memory control signal which is adapted to identify the said determined free neuron circuit. During the recognition phase, the memory control signal is thus set active only for the said determined free neuron circuit. When the neural network is structured as a chain of neuron circuits, said determined free neuron circuit is the first free in the chain. The input data bus (DATA-BUS) transporting the input vector components is connected to the weight memory of all neuron circuits. The data outputted therefrom are available on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) to properly address the weight memory and a register (253) to latch the data that are outputted on the output data bus. After this neuron circuit has been engaged, the contents of its weight memory cannot be modified any longer. To perform the pre-charge of the input vector during the recognition phase makes the engagement process more efficient and significantly reduces the learning time of the input vector.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.018 seconds)
