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    Substrate, assembly and method for wafer-to-wafer hybrid bonding
    21.
    发明授权
    Substrate, assembly and method for wafer-to-wafer hybrid bonding 有权

    公开(公告)号：US11769750B2

    公开(公告)日：2023-09-26

    申请号：US17387617

    申请日：2021-07-28

    Applicant: IMEC VZW

    Inventor： Joeri De Vos ,  Eric Beyne

    IPC: H01L23/538 ,  H01L23/00 ,  H01L27/06

    CPC classification number: H01L24/80 ,  H01L23/5385 ,  H01L23/5386 ,  H01L27/0688

    Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures. Deformation of the conductive material of the contact structures through creep pushes the material into the openings from the bottom up, thereby bringing the contact patches into mutual and conductive contact.

    Method of bonding semiconductor substrates
    22.
    发明授权
    Method of bonding semiconductor substrates 有权

    公开(公告)号：US10886252B2

    公开(公告)日：2021-01-05

    申请号：US15908641

    申请日：2018-02-28

    Applicant: IMEC VZW

    Inventor： Lan Peng ,  Soon-Wook Kim ,  Eric Beyne ,  Gerald Peter Beyer ,  Erik Sleeckx ,  Robert Miller

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/20 ,  H01J37/32

    Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

    SEMICONDUCTOR COMPONENT WITH METAL-INSULATOR-METAL CAPACITOR ASSEMBLY
    26.
    发明公开
    SEMICONDUCTOR COMPONENT WITH METAL-INSULATOR-METAL CAPACITOR ASSEMBLY 审中-公开

    公开(公告)号：US20240222260A1

    公开(公告)日：2024-07-04

    申请号：US18545256

    申请日：2023-12-19

    Applicant: IMEC VZW

    Inventor： Eric Beyne ,  Philip Nolmans ,  Kenichi Miyaguchi

    IPC: H01L23/522

    CPC classification number: H01L23/5222 ,  H01L28/87 ,  H01L28/91

    Abstract: The disclosed technology is related to semiconductor components, including a multilayer structure with a plurality of MIM capacitors. The capacitors are realized as an assembly of capacitors in the form of a stack of at least three electrically conductive layers, separated by dielectric layers and formed conformally on a topography defined by a plurality of dielectric pillars distributed on a conductive bottom plate formed on a first level of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate ayers of the stack become available for contacting the layers by via connections.

    METHOD OF PRODUCING AN INTEGRATED CIRCUIT CHIP INCLUDING A BACK-SIDE POWER DELIVERY NETWORK
    28.
    发明公开
    METHOD OF PRODUCING AN INTEGRATED CIRCUIT CHIP INCLUDING A BACK-SIDE POWER DELIVERY NETWORK 审中-公开

    公开(公告)号：US20230142597A1

    公开(公告)日：2023-05-11

    申请号：US18048005

    申请日：2022-10-19

    Applicant: IMEC VZW

    Inventor： Anabela Veloso ,  Eric Beyne ,  Anne Jourdain

    IPC: H01L21/768 ,  H01L21/66 ,  H01L21/78

    CPC classification number: H01L21/76877 ,  H01L21/78 ,  H01L21/76802 ,  H01L22/12

    Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

    Method for dicing a semiconductor substrate into a plurality of dies
    29.
    发明授权
    Method for dicing a semiconductor substrate into a plurality of dies 有权

    公开(公告)号：US11476162B2

    公开(公告)日：2022-10-18

    申请号：US17038737

    申请日：2020-09-30

    Applicant: IMEC VZW

    Inventor： Frank Holsteyns ,  Eric Beyne ,  Christophe Lorant ,  Simon Braun

    IPC: H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48

    Abstract: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

    Method for packaging semiconductor dies
    30.
    发明授权
    Method for packaging semiconductor dies 有权

    公开(公告)号：US11462420B2

    公开(公告)日：2022-10-04

    申请号：US16601436

    申请日：2019-10-14

    Applicant: IMEC vzw

    Inventor： Eric Beyne

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/473

    Abstract: A method for packaging semiconductor dies by overmolding is disclosed. The dies are embedded in a substrate of a mold material, and cavities are produced in the mold substrate by producing 3D structures of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. A conformal layer is produced on the 3D structures prior to overmolding, and the mold substrate is thinned to expose an upper surface of the 3D structures. The conformal layer is not removed when the sacrificial structures are removed. In this way, the conformal layer remains on the surfaces of the mold substrate inside the cavity. In one aspect, the conformal layer may have a protective function, useful in the production of packages including dies which come into contact with fluid substances.

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