公开(公告)号：US10886252B2

公开(公告)日：2021-01-05

申请号：US15908641

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Lan Peng ,  Soon-Wook Kim ,  Eric Beyne ,  Gerald Peter Beyer ,  Erik Sleeckx ,  Robert Miller

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/20 ,  H01J37/32

Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

公开(公告)号：US20240112944A1

公开(公告)日：2024-04-04

申请号：US18474803

申请日：2023-09-26

Applicant: IMEC VZW

Inventor： Jakob Visker ,  Lan Peng ,  Serge Vanhaelemeersch ,  Aurelie Humbert ,  Chi Dang Thi Thuy ,  Evert Visker

IPC: H01L21/683 ,  B32B43/00 ,  H01L21/30

CPC classification number: H01L21/6836 ,  B32B43/006 ,  H01L21/30

Abstract: The present disclosure relates to a temporary wafer bonding process including the steps of: providing a wafer for back processing by laminating a plain protective film on a front surface of the wafer; providing a rigid carrier; bonding the rigid carrier to the plain protective film by the intermediate of a bonding material layer; processing a back surface of the wafer; and separating the rigid carrier and the plain protective film from the wafer.

公开(公告)号：US20170301646A1

公开(公告)日：2017-10-19

申请号：US15604454

申请日：2017-05-24

Applicant: IMEC VZW

Inventor： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L21/02065 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/03845 ,  H01L2224/03848 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/32501 ,  H01L2224/80048 ,  H01L2224/80097 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83031 ,  H01L2224/83047 ,  H01L2224/83048 ,  H01L2224/83359 ,  H01L2924/00012 ,  H01L2924/0504 ,  H01L2924/00014 ,  H01L2924/20106 ,  H01L2924/2011

Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

公开(公告)号：US10141284B2

公开(公告)日：2018-11-27

申请号：US15604454

申请日：2017-05-24

Applicant: IMEC VZW

Inventor： Soon-Wook Kim ,  Lan Peng ,  Patrick Verdonck ,  Robert Miller ,  Gerald Peter Beyer ,  Eric Beyne

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/02 ,  H01L21/3105

Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

公开(公告)号：US20180247914A1

公开(公告)日：2018-08-30

申请号：US15908641

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Lan Peng ,  Soon-Wook Kim ,  Eric Beyne ,  Gerald Peter Beyer ,  Erik Sleeckx ,  Robert Miller

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/83 ,  H01J37/32091 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/2007 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83009 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2224/83986 ,  H01L2924/04642 ,  H01L2924/059 ,  H01L2924/20106 ,  H01L2924/20107

Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.