公开(公告)号：AT249664T

公开(公告)日：2003-09-15

申请号：AT00990531

申请日：2000-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

IPC: G06F12/08 ,  G06F12/14 ,  G06F21/60 ,  G06F21/85 ,  G07F7/10 ,  G11C7/24

Abstract: A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

公开(公告)号：DE10201449C1

公开(公告)日：2003-08-14

申请号：DE10201449

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLUG FRANZ ,  KNIFFLER OLIVER ,  GAMMEL BERNDT

IPC: G06F1/00 ,  G06F7/00 ,  G06F7/57 ,  G06F21/72 ,  G06F21/75 ,  G06F7/48

Abstract: A calculating unit for performing an arithmetic operation with at least two operands, the at least two operands being encrypted, includes an arithmetic-logic unit with a first input for the first encrypted operand, a second input for the second encrypted operand, a third input for an encryption parameter and an output for an encrypted result of the operation, the arithmetic-logic unit being formed so as to operate on the first input, the second input and the third input by means of arithmetic sub-operations, while considering the type of encryption of the operands, such that at the output, an encrypted result is obtained which equals a value that would be obtained if the first operand was subjected to the arithmetic operation in a non-encrypted state and if the second operand would be subjected to the arithmetic operation in a non-encrypted state, and a result obtained was subsequently encrypted, no decryption of the operands being performed in the arithmetic-logic unit. In this manner, a processor system may be obtained in which no data whatsoever occurs in clear text, i.e. in a non-encrypted form, since no decryption upstream of an arithmetic-logic unit and no encryption downstream of the arithmetic-logic unit are required, as the arithmetic-logic unit operates with encrypted input operands to obtain an encrypted result. Interception attacks on transmission lines of the calculating unit are thus ruled out.

公开(公告)号：DE10201443A1

公开(公告)日：2003-08-07

申请号：DE10201443

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLUG FRANZ ,  KNIFFLER OLIVER ,  GAMMEL BERNDT

IPC: G06F7/52 ,  G06F7/57

公开(公告)号：AU2003206709A8

公开(公告)日：2003-07-30

申请号：AU2003206709

申请日：2003-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  KNIFFLER OLIVER ,  KLUG FRANZ

IPC: G06F1/00 ,  G06F7/00 ,  G06F7/57 ,  G06F21/72 ,  G06F21/75 ,  G06F7/48

Abstract: A calculating unit for performing an arithmetic operation with at least two operands, the at least two operands being encrypted, includes an arithmetic-logic unit with a first input for the first encrypted operand, a second input for the second encrypted operand, a third input for an encryption parameter and an output for an encrypted result of the operation, the arithmetic-logic unit being formed so as to operate on the first input, the second input and the third input by means of arithmetic sub-operations, while considering the type of encryption of the operands, such that at the output, an encrypted result is obtained which equals a value that would be obtained if the first operand was subjected to the arithmetic operation in a non-encrypted state and if the second operand would be subjected to the arithmetic operation in a non-encrypted state, and a result obtained was subsequently encrypted, no decryption of the operands being performed in the arithmetic-logic unit. In this manner, a processor system may be obtained in which no data whatsoever occurs in clear text, i.e. in a non-encrypted form, since no decryption upstream of an arithmetic-logic unit and no encryption downstream of the arithmetic-logic unit are required, as the arithmetic-logic unit operates with encrypted input operands to obtain an encrypted result. Interception attacks on transmission lines of the calculating unit are thus ruled out.

公开(公告)号：AU2003205592A1

公开(公告)日：2003-07-30

申请号：AU2003205592

申请日：2003-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  KLUG FRANZ ,  KNIFFLER OLIVER

IPC: G06F5/01 ,  G06F21/72 ,  G06F7/00

Abstract: A shift device for shifting a first place of a data word, which consists of a plurality of places, to a second place so as to obtain a shifted data word, wherein the first place is encrypted using a first encryption parameter and wherein the second place is encrypted using a second encryption parameter, includes a unit for shifting the first place of the data word to the second place of the data word, a unit for re-encrypting the first place from an encryption using the first encryption parameter into an encryption using the second encryption parameter, and a control for controlling the unit for shifting and the unit for re-encryption so that the first place is first shifted to the second place and is then re-encrypted, or that the first place is first re-encrypted and is then shifted to the second place. This ensures that data encrypted either with the first encryption parameter or with the second encryption parameter are always shifted, thus making it harder for attackers to eavesdrop on clear text data.

公开(公告)号：DE50000925D1

公开(公告)日：2003-01-23

申请号：DE50000925

申请日：2000-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNIFFLER OLIVER ,  DIRSCHERL GERD

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/02 ,  G11C29/36 ,  G11C29/40

Abstract: The built-in self test method enables common and concurrent self testing of the combinatorial logic and the memory of an electronic circuit. The common self test circuit for the logic and the memory performs the self test simultaneously for the logic and for the memory.

公开(公告)号：DE10109220A1

公开(公告)日：2002-09-12

申请号：DE10109220

申请日：2001-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  HERMANN GERWIN ,  KNIFFLER OLIVER

IPC: H01L23/522 ,  H01L23/58 ,  H01L27/08

Abstract: The invention relates to an integrated circuit comprising a supply potential connection, a reference potential connection and an energy storage capacitor which is wired up between said two connections. Said energy storage capacitor consists of two conductor tracks or sections of conductor track which are coupled to each other in a capacitive manner.

公开(公告)号：DE19946716A1

公开(公告)日：2001-04-12

申请号：DE19946716

申请日：1999-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  GAERTNER WOLFGANG

IPC: G06F13/362

Abstract: The invention relates to a method for operating a processor bus with which a central unit (processor) accesses different peripheral units. The order of accesses can be altered according to the operating mode of the peripheral units and the peripheral units can either reject or defer access.

公开(公告)号：DE102005022107B4

公开(公告)日：2015-10-01

申请号：DE102005022107

申请日：2005-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GÖTTFERT RAINER ,  GAMMEL BERNDT ,  KNIFFLER OLIVER

IPC: G06F11/10 ,  H03M13/19

Abstract: In einer Vorrichtung zum Bestimmen einer Position eines Bitfehlers in einer Bitfolge wird eine Kontrollmatrix (H) verwendet, die eine vordefinierte Zeilenanzahl und eine vordefinierte Spaltenanzahl aufweist. Die Kontrollmatrix (H) umfasst eine Mehrzahl von quadratischen Teilmatrizen (A0, ..., A3), die eine Teilmatrixzeilenanzahl und eine Teilmatrixspaltenanzahl haben, die der vordefinierten Zeilenanzahl oder der vordefinierten Spaltenanzahl der Kontrollmatrix (A) entspricht. Die Vorrichtung zum Bestimmen umfasst dann eine Einrichtung (102) zum Empfangen einer Bitfolge sowie eine Einrichtung (104) zum Ermitteln eines Syndroms unter Verwendung der Kontrollmatrix (H) und der empfangenen Bitfolge (y). Ferner umfasst die Vorrichtung eine Einrichtung (106) zum Feststellen einer Position (r) eines Bitfehlers in der empfangenen Bitfolge (y), wobei die Einrichtung zum Feststellen (106) ausgebildet ist, um in dem Syndrom ein Syndrombit und eine Syndrombitgruppe zu identifizieren und wobei die Einrichtung (106) zum Feststellen ferner ausgebildet ist, um unter Verwendung einer Information über eine Position des Syndrombits oder der Syndrombitgruppe in dem Syndrom, eine Information über eine Beziehung zwischen dem Syndrombit und der Syndrombitgruppe und einer Teilmatrixzeilenanzahl oder einer Teilmatrixspaltenanzahl einer Teilmatrix die Position des Bitfehlers in der empfangenen Bitfolge zu bestimmen.

公开(公告)号：AT454670T

公开(公告)日：2010-01-15

申请号：AT00983200

申请日：2000-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

IPC: G06F12/14 ,  G06F1/00 ,  G06F15/00 ,  G06F21/12 ,  G06F21/60 ,  G06F21/85 ,  G09C1/00 ,  H04L9/20

Abstract: A microprocessor configuration includes a data bus for data transfer between functional units. On the bus side, each unit contains an encryption/decryption unit that is controlled synchronously by a random number generator. The configuration permits a relatively high level of security against monitoring of the data transferred via the data bus, with a feasible level of additional circuit complexity.