公开(公告)号：JP2006351201A

公开(公告)日：2006-12-28

申请号：JP2006271292

申请日：2006-10-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETERS CHRISTIAN ,  SEDLAK HOLGER

IPC: G11C16/04 ,  G11C16/06 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To define specifications of a floating gate memory wherein conventional issues are avoided. SOLUTION: A selection transistor (2) for a group of memory cells, preferably composed of 16 to 32 memory cells, is respectively introduced into feed lines to the memory cells (4). The selection transistor is opened to a line group for reading, while the control gates of all lines are low potential, and the current for each reading column leading through said line group is measured and stored. In a second step, a control gate (5) of the line to be read is brought to a higher reading potential and the resulting current is compared to the previous current. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2004355799A

公开(公告)日：2004-12-16

申请号：JP2004155356

申请日：2004-05-25

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチェンゲゼルシャフト

Inventor： SEDLAK HOLGER ,  KUENEMUND THOMAS

IPC: G11C11/41 ,  G06F9/30 ,  G06F21/75 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413

CPC classification number: G11C7/12 ,  G06F9/30141 ,  G06F21/75 ,  G11C7/10 ,  G11C8/08 ,  G11C11/413

Abstract: PROBLEM TO BE SOLVED: To present an integrated circuit in which charge integration has nothing to do with data even in the case of a write access operation.
SOLUTION: The integrated circuit comprising a switching device which is a switching device connected to at least one line pair to which dual rail signals are applicable, can be controlled by the signal applied to a control terminal and can be used for transmitting the dual rail signals (applied to the line pair) to the further line pair and a memory cell which is connected to a supply potential connection by the controllable switch.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：WO02082248A3

公开(公告)日：2003-07-31

申请号：PCT/DE0200821

申请日：2002-03-07

Applicant: INFINEON TECHNOLOGIES AG ,  WEDER UWE ,  SEDLAK HOLGER

Inventor： WEDER UWE ,  SEDLAK HOLGER

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/32 ,  Y02D10/152

Abstract: The invention relates to an integrated circuit comprising at least one voltage regulator, which is connected between a supply potential terminal and a reference potential terminal. The integrated circuit also has at least one useful circuit, which contains a memory and/or logic unit, whose supply potential input is coupled to the output of the voltage regulator. According to the invention, the voltage regulator can be switched off by a first switching device in a power saving mode. The supply potential input of the useful circuit is then connected to the supply potential terminal via a diode circuit.

Abstract translation: 本发明提出了具有电源电位端子与张力调节器相互连接的基准电位端子之间的至少一个集成电路，其进一步包括至少一个存储器和/或逻辑包括利用电路中，源极电势输入端耦合到所述电压调节器的输出。 根据本发明，通过第一开关装置在电压调节器的功率节省模式关闭。 利用电路的源极电位的输入，然后通过一个二极管电路到电源电位连接而连接。

公开(公告)号：WO0248845A3

公开(公告)日：2002-11-14

申请号：PCT/EP0114349

申请日：2001-12-06

Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT

Inventor： ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT

IPC: G06F7/72 ,  G06F9/38 ,  G06F21/55 ,  G06F21/72 ,  G06F1/00

CPC classification number: G06F9/3891 ,  G06F7/72 ,  G06F7/723 ,  G06F9/3879 ,  G06F9/3885 ,  G06F21/72 ,  G06F21/755 ,  G06F2207/7266

Abstract: The invention relates to a cryptographic processor comprising a central processing unit and a coprocessor, said coprocessor having a large number of arithmetic subunits and a single control unit, which is coupled to each of the arithmetic subunits. The control unit divides a cryptographic operation among the individual subunits in the form of suboperations. The central processing unit, the large number of arithmetic subunits and the control unit are integrated into a single chip, said chip having a common power supply input for supplying the large number of arithmetic subunits and the control unit with current. The arrangement in series of different arithmetic subunits increases the throughput of the cryptographic processor and randomises the current profile, which can be detected at the power supply input, in such a way that it is impossible for an attacker to deduce the characters that are being processed in the individual arithmetic subunits.

Abstract translation: 密码处理器包括中央处理单元和协处理器，协处理器具有多个子阵列和耦合到多个子阵列中的每一个的单个控制器。 密码操作由控制单元以子操作的形式分配给各个子处理器。 中央处理单元，多个子阵列和控制单元集成在单个芯片上，该芯片具有用于为多个子阵列和控制单元供电的公共电源电流通路。 一方面，通过部分计算单元的并行布置来增加密码处理器的吞吐量。 但是，另一方面，在供电电流存取中可以检测到的当前配置文件也是随机的，这样攻击者就不能再推断单个部分计算中处理的数字。

公开(公告)号：WO03048943A2

公开(公告)日：2003-06-12

申请号：PCT/DE0204066

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT M ,  KUENEMUND THOMAS ,  SEDLAK HOLGER

Inventor： GAMMEL BERNDT M ,  KUENEMUND THOMAS ,  SEDLAK HOLGER

IPC: G06F12/0804 ,  G06F12/14 ,  G06F21/24 ,  H04L9/10 ,  G06F1/00 ,  G06F12/08

CPC classification number: G06F12/1408 ,  G06F12/0804

Abstract: The invention relates to a memory, especially a cache memory, and a method for synchronising said cache memory with the main memory of a computer. According to the inventive method, each memory entry has an address range, a data area which is associated with the address range, and an identification area which is associated with the address range. Said identification area has a first memory field containing a value which indicates whether data is stored in the data area of the memory or with which cryptographic key. The information contained in the first memory field can be used as a starting point for synchronisation, on the basis of an accepted association between the data to be synchronised and the cryptographic keys.

Abstract translation: 本发明提出一种存储器，特别是高速缓冲存储器，和同步高速缓冲存储器的计算机系统的主存储器的一种方法，其中具有地址范围内的每个存储条目，所分配的地址范围的数据区，和与所述地址空间标识符字段相关联。 在这种情况下的识别区包括第一存储器阵列包括一个值，指示加密密钥数据是否与存储在存储器中的数据区域。 由于推定数据和加密密钥同步之间的关联，包含在第一存储器字段中的信息可以作为同步的基准。

公开(公告)号：WO02073394A3

公开(公告)日：2002-11-07

申请号：PCT/EP0200734

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT ,  SEIFERT JEAN-PIERRE

Inventor： ELBE ASTRID ,  SEDLAK HOLGER ,  JANSSEN NORBERT ,  SEIFERT JEAN-PIERRE

IPC: G06F7/00 ,  G06F7/72 ,  G09C1/00

CPC classification number: G06F7/722

Abstract: The invention relates to a method for modular multiplication using a multiplication prediction process for calculating a multiplication shift value and a reduction prediction process for calculating a reduction shift value. According to said method, a modulus is first transformed (10) into a transformed modulus, which is greater than the modulus. The transformation is carried out in such a way that a predefined portion of the transformed modulus has a higher order position with a first predefined value, which is followed at least by a lower order position with a second predefined value. During the iterative processing (12) of the modular multiplication using the multiplication prediction process and the reduction prediction process, the transformed modulus is used to obtain a transformed result for the modular multiplication at the end of the iteration. Finally, the transformed result undergoes an inverse transform (14) by means of modular reduction using the original modulus. The inventive transformation simplifies the iterative processing of the modular multiplication, enabling the latter to be carried out more rapidly.

Abstract translation: 模块化MultiplizierenBei方法和装置中使用乘法先行方法用于计算乘法移位值和计算减少移位值的减少先行方法模乘的方法是首先变换成经变换的模量的模块（10） 这比模块大。 该变换中进行，使得具有具有第一预定值，其为至少遵循具有第二预定值的少显著位更显著数字变换模量的​​预定分数。 期间使用所述乘法的先行处理的模乘和模数转换的还原先行方法的迭代工作关（12）被用于获得变换结果为在迭代结束时的模乘。 最后，转换后的结果通过使用原始模量（14）的模块化缩减重新形成。 根据本发明的改造，模乘的迭代处理被简化，从而使模乘可以更快地执行。

公开(公告)号：WO02057906A3

公开(公告)日：2002-11-07

申请号：PCT/DE0200093

申请日：2002-01-15

Applicant: INFINEON TECHNOLOGIES AG ,  MAY CHRISTIAN ,  SEDLAK HOLGER

Inventor： MAY CHRISTIAN ,  SEDLAK HOLGER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/305 ,  G06F9/42 ,  G06K19/07

CPC classification number: G06F9/30105 ,  G06F9/30127 ,  G06F9/30134

Abstract: The invention relates to a microprocessor circuit comprising a control unit, a memory for free programming with at least one program comprising functions, a stack for the intermediate storage of data and a register bank comprising at least one register which contains an auxiliary register storing a number of bits. Each bit is associated with one of the registers in the register bank and indicates whether or not each register in the register bank contains information.

Abstract translation: 本发明提出了具有控制单元，用于与具有程序的至少一个功能，用于缓冲存储数据和至少一个具有寄存器组寄存器之前的堆叠，其进一步包含Hilfsre-gister包含在多个自由编程存储器的微处理器电路 位存储，其中，每个-的比特被分配给寄存器组的寄存器中的一个，并且指示所述寄存器组中的相应寄存器中是否包含信息或没有。

公开(公告)号：WO0248857A3

公开(公告)日：2002-09-19

申请号：PCT/EP0113279

申请日：2001-11-16

Applicant: INFINEON TECHNOLOGIES AG ,  ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

Inventor： ELBE ASTRID ,  JANSSEN NORBERT ,  SEDLAK HOLGER

IPC: G06F15/78 ,  G06F7/72 ,  H04L9/10 ,  H04L9/14 ,  G06F1/00

CPC classification number: G06F7/72 ,  G06F2207/7223 ,  G06F2207/7266

Abstract: The invention relates to a cryptographic processor for carrying out operations for cryptographic applications and comprising a large number of coprocessors (104a, 104b, 104c), each coprocessor having a control unit and an arithmetic unit, a central processing unit (102) for controlling the large number of coprocessors (104a, 104b, 104c) and a bus (101) for connecting each coprocessor (104a, 104b, 104c) to the central processing unit (102). The central processing unit (102), the majority of coprocessors (104a, 104b, 104c) and the bus (101) are integrated into a single chip (100). The chip also comprises a common power supply input (122) for supplying the large number of coprocessors (104a, 104b, 104c). The connection in series of different coprocessors increases the throughput of the cryptographic processor and simultaneously improves the security of said processor against attacks, made on the basis of an evaluation of output profiles of the cryptographic processor, as the output profiles of at least two coprocessors are superimposed. By using different types of coprocessors, the cryptographic processor can also be configured as a multifunctional cryptographic processor suitable for use with a multitude of different cryptographic algorithms.

Abstract translation: 用于加密应用程序执行操作的密码处理器包括：多个协处理器（104A，104B，104C），每个协处理器具有控制单元和算术单元，用于驱动一个中央处理单元（102），所述多个协处理器（104A，104B， 104C）和用于连接每个协处理器（104A，104B，104C）输出到总线（101），所述中央处理单元（102）。 中央处理单元（102），所述多个协处理器（104A，104B，104C）和总线（101）的是一个单一的芯片（100）被集成在。 该芯片还包括用于提供所述多个协处理器（104A，104B，104C）的公共电源电流访问（122）。 在吞吐量和同时改善密码处理器的攻击的安全性的增加是通过各种协处理器，其基于的密码处理器的性能概况评估的并行连接来实现，因为至少两个协处理器的功率分布重叠。 此外，密码处理器，也可以通过使用各种协处理器作为多功能密码处理器为适合于各种不同的密码算法配置。

公开(公告)号：WO2004068345A3

公开(公告)日：2007-11-29

申请号：PCT/DE2004000127

申请日：2004-01-28

Applicant: INFINEON TECHNOLOGIES AG ,  MAY CHRISTIAN ,  NOLLES JUERGEN ,  SEDLAK HOLGER

Inventor： MAY CHRISTIAN ,  NOLLES JUERGEN ,  SEDLAK HOLGER

IPC: G06F11/36

CPC classification number: G06F11/3648

Abstract: The invention relates to a method for controlling the interrupt process and/or recording of execution data of a program in a microcontroller (1), whereby a debugging unit (3) is informed by way of a selection attribute associated with a defined program instruction whether a program may be interrupted and/or the pertaining execution data may be recorded while a program instruction is being executed. The invention also relates to a microcontroller (1) which, in addition to the switching circuits and data memories of a microcontroller (2) to be emulated, comprises an arrangement for controlling the interrupt process and/or recording of execution data of a program. The arrangement is characterized in that it comprises a debugging unit (3) and a control logic (5). Said control logic (5) uses a defined selection attribute associated with defined program instructions for deciding whether, in place of a program instruction in a program, the program flow is interrupted and/or the execution data are recorded.

Abstract translation: 本发明涉及一种方法，用于控制中断和/或程序的示例性数据的记录中的微控制器（1），由一个特定的程序指令相关联的选择正在通信属性的调试单元（3）是否在当前执行的程序指令的程序 可能被中断和/或相关联的设计数据被记录。 此外，本发明涉及一种微控制器（1）中，除了上述的电路和数据存储仿真Mikroconrollers（2）具有用于控制中断和/或程序的示例性数据的记录的装置，所述装置包括一个调试单元（3 ）和控制逻辑（5），并且所述控制逻辑（5）的基础上的特定节目的命令相关联的选择属性控制程序是否是在程序中的程序指令的位置被中断和/或性能的数据被记录。

公开(公告)号：WO2005008774A3

公开(公告)日：2005-08-11

申请号：PCT/DE2004001365

申请日：2004-06-29

Applicant: INFINEON TECHNOLOGIES AG ,  ENGL KORBINIAN ,  SEDLAK HOLGER ,  SIMONS PETER ,  UFFMANN DIRK

Inventor： ENGL KORBINIAN ,  SEDLAK HOLGER ,  SIMONS PETER ,  UFFMANN DIRK

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L23/62

CPC classification number: H01L23/60 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a semiconductor chip in which the terminal contact areas (1) and a strip conductor (2) providing ESD protection are grouped together in a narrowly confined zone (3) by passing the contact wires (4) to additional terminal contact areas (5) of a housing via at least two edges of the chip so as to save on the surface required.

Abstract translation: 端子接触表面（1）和提供用于ESD保护导体（2）被分组以面对保存在狭窄的区域（3）中，当键合线（4）的另一端的接触表面（5）的壳体在芯片的至少两个边缘的 引导。