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    Controller with decoding means
    1.
    发明专利
    Controller with decoding means 审中-公开
    具有解码手段的控制器

    公开(公告)号：JP2005339540A

    公开(公告)日：2005-12-08

    申请号：JP2005145127

    申请日：2005-05-18

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： KLUG FRANZ ,  KNIFFLER OLIVER ,  SONNEKALB STEFFEN ,  WENZEL ANDREAS

    IPC: G06F9/30 ,  G06F9/318

    CPC classification number: G06F9/30181

    Abstract: PROBLEM TO BE SOLVED: To provide a flexible controller with decoding means and a decoding method.
    SOLUTION: The controller includes a receiving means 102 receiving an executable command or a wild card command. The decoding means 104 is adapted to output, in response to the executable command, a control signal corresponding to the executable command, and output, on receipt of the wild card command, a switching signal 118 in response thereto. The controller further includes a supplying means 106 for transmitting a predetermined substitution signal 120, and the supplying means transmits the predetermined substitution control signal 120 according to the switching signal 118.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有解码装置和解码方法的灵活控制器。 解决方案：控制器包括接收可执行命令或通配符命令的接收装置102。 解码装置104适于响应于可执行命令输出与可执行命令相对应的控制信号，并且在接收到通配符命令时输出响应于此的切换信号118。 控制器还包括用于发送预定替代信号120的供应装置106，并且提供装置根据切换信号118发送预定的替换控制信号120.版权所有：（C）2006，JPO＆NCIPI

    DEVICE AND METHOD FOR MULTIPLYING OR DIVIDING A FIRST OPERAND BY A SECOND OPERAND
    2.
    发明申请
    DEVICE AND METHOD FOR MULTIPLYING OR DIVIDING A FIRST OPERAND BY A SECOND OPERAND 审中-公开
    DEVICE AND METHOD FOR乘或除第一操作数与OR 由第二个操作数

    公开(公告)号：WO03060693A2

    公开(公告)日：2003-07-24

    申请号：PCT/EP0300182

    申请日：2003-01-10

    Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT ,  KLUG FRANZ ,  KNIFFLER OLIVER

    Inventor： GAMMEL BERNDT ,  KLUG FRANZ ,  KNIFFLER OLIVER

    IPC: G06F7/52 ,  G06F21/72 ,  G06F7/00

    CPC classification number: G06F7/52 ,  G06F21/72 ,  G06F2207/7238

    Abstract: Disclosed are a device and a method for multiplying or dividing a first operand by a second operand. Secure arithmetic units used for dividing and multiplying are provided with a control unit (18) which carries out the bit analyses required for the radix-2 multiplication algorithm, booth-recoding multiplication algorithm, restoring division algorithm, and non-restoring division algorithm in the cryptographic area, using coded bits and coding parameters for coding said bits. Registers (16, 22, 24, 30) in which coded operands are stored and an adder (10) using coded operands to add and producing a coded result can also be used. Such a multiplier/divider operates in the cryptographic area and is less prone to physical and/or indirect attacks.

    Abstract translation: 的装置和方法使用控制器18，用于radix-2乘法算法，布斯重编码乘法算法中，恢复除法算法乘或除第一操作数具有或由第二操作数除法和乘法安全运算单元和 使用加密的比特，和加密参数，这些位的加密在密文空间执行非恢复除法算法必要Bituntersuchungen。 此外，可以是22，24，30个使用寄存器16，在该操作数加密存储，并且另外一个加法器10可以被使用，当被添加到加密的操作数，并提供一个编码结果。 这样的乘法器/除法器的工作原理在密文的空间和更不易于物理和/或间接的攻击。

    BUS SYSTEM COMPRISING AN ADDRESS/DATA BUS WHICH CAN BE OPERATED IN A MULTIPLEX MODE AND CONTROL BUS RESPONDING TO A STATION BY ALLOCATING A LOGICAL CHANNEL
    4.
    发明申请
    BUS SYSTEM COMPRISING AN ADDRESS/DATA BUS WHICH CAN BE OPERATED IN A MULTIPLEX MODE AND CONTROL BUS RESPONDING TO A STATION BY ALLOCATING A LOGICAL CHANNEL 审中-公开
    具有多重运行总线系统来操作地址/数据总线和控制总线来操作站通过分配的逻辑信道的

    公开(公告)号：WO02075551A3

    公开(公告)日：2003-08-28

    申请号：PCT/DE0200549

    申请日：2002-02-15

    Applicant: INFINEON TECHNOLOGIES AG ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

    Inventor： KNIFFLER OLIVER ,  SEDLAK HOLGER

    IPC: G06F13/42

    CPC classification number: G06F13/4217

    Abstract: The invention relates to a data bus which can be operated in a multiplex mode, whereby at least one control station and a receiving station are connected thereto. A control bus is also provided, through which a logical channel is allocated by the control station to the receiving station. Once logical channel has been allocated, the address does not have to be transferred via the data bus before the receiving station is next addressed. The receiving station monitors the control bus and is addressed so that the allocated logical channel of the receiving station is opened therewith.

    Abstract translation: 它是在一个多路复用数据总线可操作提供，在其上至少一个控制站和接收站连接。 有另外从控制站到接收站提供的控制总线，逻辑信道可以在所分配的。 如果分配一旦做出，必须为地址经由数据总线接收站不仅下一激活之前被发送。 接收站监视控制总线和被寻址尽快与该接收站逻辑信道是开放的分配。

    MICROPROCESSOR SYSTEM AND METHOD FOR OPERATING A MICROPROCESSOR SYSTEM
    5.
    发明申请
    MICROPROCESSOR SYSTEM AND METHOD FOR OPERATING A MICROPROCESSOR SYSTEM 审中-公开
    微处理器安排和方法操作微处理器安排

    公开(公告)号：WO0153931A3

    公开(公告)日：2001-12-20

    申请号：PCT/DE0100018

    申请日：2001-01-05

    Applicant: INFINEON TECHNOLOGIES AG ,  GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

    Inventor： GAMMEL BERNDT ,  KNIFFLER OLIVER ,  SEDLAK HOLGER

    IPC: G06F12/08 ,  G06F12/14 ,  G06F15/78 ,  G06F21/75

    CPC classification number: G06F21/75 ,  G06F12/1408

    Abstract: A microprocessor system wherein data is temporarily stored in a cache memory (8) or a register bank (9). A respectively allocated cryptographic unit (81, 82; 91) is responsible for encrypting/decrypting the data when the cache memory (8) or register bank is accessed. The code word used therefor is modified when the cache memory (8) or register (9) no longer contains any data which is to be read. This results in increased security with respect to unauthorized access to data and program execution.

    Abstract translation: 在微处理器中的配置数据被暂时存储在高速缓冲存储器（8）或寄存器组（9）。 甲分别相关联的加密单元（81，82; 91）提供在到高速缓冲存储器（8）或寄存器组（9）的访问的数据的加密/解密。 当要读出的高速缓冲存储器（8）或寄存器（9）不包含有效数据的详细这里使用的密钥字被改变。 这提供了防止间谍更高的安全性上的数据，并且获得的程序流。

    METHOD FOR OPERATING A MICROPROCESSOR SYSTEM AND A CORRESPONDING MICROPROCESSOR SYSTEM
    6.
    发明申请
    METHOD FOR OPERATING A MICROPROCESSOR SYSTEM AND A CORRESPONDING MICROPROCESSOR SYSTEM 审中-公开
    方法操作微处理器安排和单片机安排

    公开(公告)号：WO0153930A3

    公开(公告)日：2001-12-06

    申请号：PCT/DE0100155

    申请日：2001-01-16

    Applicant: INFINEON TECHNOLOGIES AG ,  KNIFFLER OLIVER

    Inventor： KNIFFLER OLIVER

    IPC: G06F13/36 ,  G06F1/00 ,  G06F12/14 ,  G06F21/55 ,  G06F21/75 ,  G06K19/073

    CPC classification number: G06K19/073 ,  G06F12/1408 ,  G06F21/75 ,  G06F21/755 ,  G06F2207/7219 ,  G06F2221/2123 ,  G06K19/07363

    Abstract: The invention relates to a microprocessor system comprising a central control and processing unit (1), a bus (2) with a bus status line (21) and data/address lines (22), and comprising units (3, 4, 5) connected to the bus (2). When none of the units (3, 4, 5) are actuated by the control and processing unit (1), random data values (12) are transmitted to the data/address lines (22). This enables the profile of the current of the microprocessor system to be concealed with regard to the useful information to be transmitted via the bus (2).

    Abstract translation: 一个微处理器装置，其包括一个中央控制和处理单元（1），总线（2）与Buszustandsleitung（21）和数据/地址线（22）和（2）连接到单元的总线（3，4，5）。 如果没有单元（3，4，5）由控制和处理单元（1）所提到的，随机的数据值（12）被转移到数据/地址线（22）。 因而，微处理器装置的电流分布被掩蔽相对于过（2）将要发送的有效载荷的总线。

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