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公开(公告)号：GB2419986A
公开(公告)日：2006-05-10
申请号：GB0601321
申请日：2003-03-20
Applicant: INTEL CORP
Inventor： SUTTON JAMES , GRAWROCK DAVID
Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialisation and secure virtual machine monitor software into memory. The initiating processor then loads the initialisation software into secure memory for authentication and execution. The initialisation software then authenticates and registers the secure virtual machine monitor software prior to secure system operations. Executing a secured enter instruction, receiving a special bus message and setting a flag.
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公开(公告)号：AU2003222104A1
公开(公告)日：2003-11-03
申请号：AU2003222104
申请日：2003-03-28
Applicant: INTEL CORP
Inventor： GRAWROCK DAVID , SUTTON JAMES II
Abstract: In one embodiment, a method comprises generating a cryptographic key pair associated with a data center. The method also includes storing a private key of the cryptographic key pair within a platform. The private key is used to sign a value stored in the platform for validation of inclusion of the platform into the data center. In an embodiment, the private key is revoked upon determining that the platform has been compromised. In one embodiment, the private key may be revoked in each of the platforms of the data center.
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公开(公告)号：DE112010006087T5
公开(公告)日：2014-06-26
申请号：DE112010006087
申请日：2010-12-23
Applicant: INTEL CORP
Inventor： TIRUVALLUR KRESHAVAN , LOVIN CHRISTIAN , GRAWROCK DAVID , HALPRIN EVAN J , FOO JIUN LONG , CHEAH WEE HOO , YONG VUI , LEE YEN TAT , KILLPACK KIP , DOBLER NIEL , HAKIM NAGIB Z , WHITE MICHAEL T , MEYER BRIAN , WUNDERLICH RUSS , KOZACZUK ANTHONY , MARKLEY KYLE , MCCONNELL LOREN , COOL LYLE , MOHAMMED RAHIMA , ZHENG TIEYU , PRUDVI CHINNA , GOPAL SELVAKUMAR RAJA , PENNER BILL , STOREY TIM , KATARIA MUKESH , SAHA RIDVAN , GOFF TRAVIS , BAUDREXL JOHN , GREALISH JAMES , XIA AMY , SAMAAN SAMIE B , UDAWATTA KAPILA , KABADI ASHOK , NEJEDLO JAY , TROBOUGH MARK
Abstract: Eine Vorrichtung und ein Verfahren zum Bereitstellen einer Architektur zum Testen, zur Validierung und zur Fehlerbereinigung werden hierin beschrieben. Auf einer Ziel- oder Basisebene werden Hardwarehaken (Design-For-Test oder DFx) in Siliziumbauteilen angeordnet und in diese integriert. Ein Controller kann einen abstrahierten Zugriff auf solche Haken beispielsweise über eine Abstraktionsschicht, welche Details der Hardware-DFx auf niedriger Ebene abstrahiert, bereitstellen. Zusätzlich stellt die Abstraktionsschicht durch eine Schnittstelle, wie beispielsweise APIs, Dienste, Routinen und Datenstrukturen für Software-/Präsentationsschichten auf höheren Ebenen bereit, welche dazu in der Lage sind, Testdaten für eine Validierung und eine Fehlerbereinigung einer Einheit/Plattform im Test zu sammeln. Ferner stellt die Architektur der Testarchitektur potentiell einen abgestuften sicheren (mehrere Ebenen von sicherem) Zugriff bereit. Zusätzlich kann ein physikalischer Zugriff auf die Testarchitektur für eine Plattform durch das Verwenden eines vereinheitlichten, bi-direktionalen Testzugriffanschlusses vereinfacht werden, wobei auch potentiell ein Fernzugriff erlaubt wird, um ein Testen und eine Fehlerbereinigung eines Bauteils/einer Plattform im Test aus der Ferne zu ermöglichen. Im Wesentlichen wird hierin ein vollständiger Testarchitekturstapel zum Testen, zur Validierung und zur Fehlerbereinigung elektronischer Bauteile, Einrichtungen und Plattformen beschrieben.
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公开(公告)号：GB2493793A
公开(公告)日：2013-02-20
申请号：GB201122290
申请日：2010-12-23
Applicant: INTEL CORP
Inventor： TROBOUGH MARK B , TIRUVALLUR KRESHAVAN , PRUDVI CHINNA , LOVIN CHRISTIAN , GRAWROCK DAVID , NEJEDLO JAY , KABADI ASHOK , GOFF TRAVIS , HALPRIN EVAN J , UDAWATTA KAPILA , FOO JIUN LONG , CHEAH WEE HOO , YONG VUI , GOPAL SELVAKUMAR RAJA , LEE YEN TAT , SAMAAN SAMIE B , KILLPACK KIP , DOBLER NIEL , HAKIM NAGIB Z , WHITE MICHAEL T , MEYER BRIAN , PENNER BILL , BAUDREXL JOHN , WUNDERLICH RUSS , KOZACZUK ANTHONY , GREALISH JAMES , MARKLEY KYLE , STOREY TIM , MCCONNELL LOREN , COOL LYLE , KATARIA MUKESH , MOHAMMED RAHIMA , ZHENG TIEYU , XIA AMY , SAHA RIDVAN
IPC: G06F11/36
Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
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公开(公告)号：DE10392320B4
公开(公告)日：2011-02-24
申请号：DE10392320
申请日：2003-02-13
Applicant: INTEL CORP
Inventor： SUTTON JAMES II , KOZUCH MICHAEL , GRAWROCK DAVID
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Patent Agency Ranking
公开(公告)号：AT460709T
公开(公告)日：2010-03-15
申请号：AT03718090
申请日：2003-03-28
Applicant: INTEL CORP
Inventor： SUTTON JAMES , GRAWROCK DAVID
Abstract: In one embodiment, a method comprises generating a cryptographic key pair associated with a data center. The method also includes storing a private key of the cryptographic key pair within a platform. The private key is used to sign a value stored in the platform for validation of inclusion of the platform into the data center. In an embodiment, the private key is revoked upon determining that the platform has been compromised. In one embodiment, the private key may be revoked in each of the platforms of the data center.
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公开(公告)号：GB2430127B
公开(公告)日：2008-12-31
申请号：GB0700524
申请日：2005-07-08
Applicant: INTEL CORP
Inventor： SUTTON JAMES II , BRICKELL ERNEST , HALL CLIFFORD , GRAWROCK DAVID
Abstract: Delivering a Direct Proof private key to a device installed in a client computer system in the field may be accomplished in a secure manner without requiring significant non-volatile storage in the device. A unique pseudo-random value is generated and stored in the device at manufacturing time. The pseudo-random value is used to generate a symmetric key for encrypting a data structure holding a Direct Proof private key and a private key digest associated with the device. The resulting encrypted data structure is stored on a protected on-line server accessible by the client computer system.
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公开(公告)号：GB2430127A
公开(公告)日：2007-03-14
申请号：GB0700524
申请日：2005-07-08
Applicant: INTEL CORP
Inventor： SUTTON JAMES II , BRICKELL ERNEST , HALL CLIFFORD , GRAWROCK DAVID
Abstract: Delivering a Direct Proof private key to a device installed in a client computer system in the field may be accomplished in a secure manner without requiring significant non-volatile storage in the device. A unique pseudo-random value is generated and stored in the device at manufacturing time. The pseudorandom value is used to generate a symmetric key for encrypting a data structure holding a Direct Proof private key and a private key digest associated with the device. The resulting encrypted data structure is stored on a protected on-liner server accessible by the client computer system. When the device is initialized on the client computer system, the system checks if a localized encrypted data structure is present in the system. If not, the system obtains the associated encrypted data structure from the protected on-line server using a secure protocol. The device decrypts the encrypted data structure using a symmetric key regenerated from its stored pseudo-random value to obtain the Direct Proof private key. If the private key is valid, it may be used for subsequent authentication processing by the device in the client computer system.
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公开(公告)号：GB2419986B
公开(公告)日：2006-09-27
申请号：GB0601321
申请日：2003-03-20
Applicant: INTEL CORP
Inventor： SUTTON JAMES , GRAWROCK DAVID
Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
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公开(公告)号：GB2419987A
公开(公告)日：2006-05-10
申请号：GB0601322
申请日：2003-03-20
Applicant: INTEL CORP
Inventor： SUTTON JAMES , GRAWROCK DAVID
Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialisation and secure virtual machine monitor software into memory. The initiating processor then loads the initialisation software into secure memory for authentication and execution. The initialisation software then authenticates and registers the secure virtual machine monitor software prior to secure system operations. Preparing for secure operations in response to a bus message from a processor executing a secured enter instruction, and storing an acknowledgement to the bus message.
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