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21.发明申请公开(公告)号：US20200258287A1
公开(公告)日：2020-08-13
申请号：US16791719
申请日：2020-02-14
Applicant: Intel Corporation
Inventor： Ingo WALD , Gabor LIKTOR , Carsten BENTHIN , Carson BROWNLEE , Johannes GUENTHER , Jefferson D. AMSTUTZ
Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
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公开(公告)号：US20200211264A1
公开(公告)日：2020-07-02
申请号：US16236041
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott JANUS , Prasoonkumar SURTI , Karthik VAIDYANATHAN , Carsten BENTHIN , Philip LAWS
Abstract: Apparatus and method for ray tracing acceleration using a grid primitive. For example, one embodiment of an apparatus comprises: a grid primitive generator to generate a grid primitive comprising a plurality of adjacent interconnected primitives; a bitmask generator to generate a bitmask associated with the grid primitive, the bitmask comprising a plurality of bitmask values, each mask value associated with a primitive of the grid primitive; a ray tracing engine comprising traversal and intersection hardware logic to perform traversal and intersection operations in which rays are traversed through a hierarchical acceleration data structure and intersections between the rays and one or more of the adjacent interconnected primitives identified, wherein the ray tracing engine is to read the bitmask to determine a first set of primitives from the grid primitive on which to perform the traversal and intersection operations and a second set of primitives from the grid primitive on which the traversal and intersection operations will not be performed.
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23.发明申请公开(公告)号：US20190228560A1
公开(公告)日：2019-07-25
申请号：US16252414
申请日：2019-01-18
Applicant: Intel Corporation
Inventor： Ingo WALD , Gabor LIKTOR , Carsten BENTHIN , Carson BROWNLEE , Johannes GUENTHER , Jefferson D. AMSTUTZ
Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
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24.发明公开公开(公告)号：US20240046547A1
公开(公告)日：2024-02-08
申请号：US18228777
申请日：2023-08-01
Applicant: INTEL CORPORATION
Inventor： Ingo WALD , Carsten BENTHIN , Sven WOOP
CPC classification number: G06T15/06 , G06T7/50 , G06T15/005 , G06T15/506 , G06T1/20
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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25.发明公开公开(公告)号：US20230298255A1
公开(公告)日：2023-09-21
申请号：US17699064
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Carsten BENTHIN , Radoslaw DRABINSKI , Joshua BARCZAK , Sven WOOP , Holger H. GRUEN , Pawel MAJEWSKI
CPC classification number: G06T15/06 , G06T15/005 , G06T17/005 , G06T7/70
Abstract: Apparatus and method for camera-aware BVH re-braiding. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH); and BVH processing hardware logic to modify the BVH to reduce spatial overlap between one or more BVH subtrees based on a detected camera position to produce a modified BVH.
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Patent Agency Ranking
公开(公告)号：US20230298254A1
公开(公告)日：2023-09-21
申请号：US17699060
申请日：2022-03-18
Applicant: INTEL CORPORATION
Inventor： Carsten BENTHIN , Radoslaw J. DRABINSKI , Michael DOYLE , Josh BARCZAK
CPC classification number: G06T15/06 , G06T15/08 , G06T17/10 , G06T2210/12
Abstract: Apparatus and method for accelerating bounding box merge operations. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH), the BVH comprising a plurality of axis-aligned bounding boxes (AABBs); and a bounding box (BB) merge accelerator coupled to one or more execution units and coupled to a local memory in which to store a group of the AABBs, the BB merge accelerator, in response to the one or more EUs, to determine a second AABB to merge with a first AABB in accordance with a specified distance function.
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公开(公告)号：US20230016642A1
公开(公告)日：2023-01-19
申请号：US17868610
申请日：2022-07-19
Applicant: INTEL CORPORATION
Inventor： Sven WOOP , Attila AFRA , Carsten BENTHIN , Ingo WALD , Johannes GUENTHER
Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US20220343554A1
公开(公告)日：2022-10-27
申请号：US17740754
申请日：2022-05-10
Applicant: INTEL CORPORATION
Inventor： Carson BROWNLEE , Carsten BENTHIN , Joshua BARCZAK , Kai XIAO , Michael APODACA , Prasoonkumar SURTI , Thomas RAOUX
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US20210287428A1
公开(公告)日：2021-09-16
申请号：US16819114
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Sven WOOP , Carsten BENTHIN , Karthik VAIDYANATHAN
Abstract: Apparatus and method for processing motion blur operations. For example, one embodiment of a graphics processing apparatus comprises: a bounding volume hierarchy (BVH) generator to build a BVH comprising hierarchically-arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes; and motion blur processing hardware logic to determine motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node and to map linear bounds of each of the child nodes to the quantization grid.
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公开(公告)号：US20210082154A1
公开(公告)日：2021-03-18
申请号：US17003040
申请日：2020-08-26
Applicant: INTEL CORPORATION
Inventor： Carson BROWNLEE , Carsten BENTHIN , Joshua BARCZAK , Kai XIAO , Michael APODACA , Prasoonkumar SURTI , Thomas RAOUX
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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