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公开(公告)号：US11562468B2
公开(公告)日：2023-01-24
申请号：US17171925
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Carson Brownlee , Ingo Wald , Attila Afra , Johannes Guenther , Jefferson Amstutz , Carsten Benthin
Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.
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公开(公告)号：US20220366634A1
公开(公告)日：2022-11-17
申请号：US17746691
申请日：2022-05-17
Applicant: Intel Corporation
Inventor： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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公开(公告)号：US11341709B2
公开(公告)日：2022-05-24
申请号：US16585880
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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公开(公告)号：US11335035B2
公开(公告)日：2022-05-17
申请号：US17003040
申请日：2020-08-26
Applicant: INTEL CORPORATION
Inventor： Carson Brownlee , Carsten Benthin , Joshua Barczak , Kai Xiao , Michael Apodaca , Prasoonkumar Surti , Thomas Raoux
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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25.发明申请公开(公告)号：US20220068009A1
公开(公告)日：2022-03-03
申请号：US17473770
申请日：2021-09-13
Applicant: INTEL CORPORATION
Inventor： Ingo Wald , Carsten Benthin , Sven Woop
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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Patent Agency Ranking
26.发明授权公开(公告)号：US11210841B2
公开(公告)日：2021-12-28
申请号：US16803614
申请日：2020-02-27
Applicant: Intel Corporation
Inventor： Carsten Benthin , Gabor Liktor
Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
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公开(公告)号：US11062500B2
公开(公告)日：2021-07-13
申请号：US16236041
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Philip Laws
Abstract: Apparatus and method for ray tracing acceleration using a grid primitive. For example, one embodiment of an apparatus comprises: a grid primitive generator to generate a grid primitive comprising a plurality of adjacent interconnected primitives; a bitmask generator to generate a bitmask associated with the grid primitive, the bitmask comprising a plurality of bitmask values, each mask value associated with a primitive of the grid primitive; a ray tracing engine comprising traversal and intersection hardware logic to perform traversal and intersection operations in which rays are traversed through a hierarchical acceleration data structure and intersections between the rays and one or more of the adjacent interconnected primitives identified, wherein the ray tracing engine is to read the bitmask to determine a first set of primitives from the grid primitive on which to perform the traversal and intersection operations and a second set of primitives from the grid primitive on which the traversal and intersection operations will not be performed.
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公开(公告)号：US10719974B1
公开(公告)日：2020-07-21
申请号：US16367062
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Sven Woop , Carsten Benthin
Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes; and traversal tracking circuitry to maintain a path encoding array to store path data related to the current traversal path, the path data comprising an index of a currently traversed child node; wherein the traversal/intersection circuitry is to prevent one or more subsequent rays from re-intersecting primitives from which they originated and/or avoid re-traversing the current traversal path based on the path data in the path encoding array.
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公开(公告)号：US20180286105A1
公开(公告)日：2018-10-04
申请号：US15477019
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
CPC classification number: H04N5/23212 , G02B27/017 , G06K9/00765 , G06T15/005 , H04N13/239 , H04N13/344
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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公开(公告)号：US09928640B2
公开(公告)日：2018-03-27
申请号：US14975294
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Sven Woop , Carsten Benthin , Rasmus Barringer , Tomas G. Akenine-Moller
CPC classification number: G06T15/06 , G06T15/005 , G06T15/08 , G06T2210/08 , G06T2210/12
Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
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