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    Cloud-based realtime raytracing
    2.
    发明授权
    Cloud-based realtime raytracing 有权

    公开(公告)号：US11069123B2

    公开(公告)日：2021-07-20

    申请号：US16236218

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Carson Brownlee ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Philip Laws ,  Thomas Raoux ,  Travis Schluessler

    IPC: G06T15/06 ,  G06T15/00

    Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.

    Context-aware compression with quantization of hierarchical transform matrices
    3.
    发明授权
    Context-aware compression with quantization of hierarchical transform matrices 有权

    公开(公告)号：US10762668B2

    公开(公告)日：2020-09-01

    申请号：US16235672

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Carson Brownlee ,  Carsten Benthin ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Prasoonkumar Surti ,  Thomas Raoux

    IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

    Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

    Apparatus and method for ray tracing instruction processing and execution
    6.
    发明授权
    Apparatus and method for ray tracing instruction processing and execution 有权

    公开(公告)号：US12236519B2

    公开(公告)日：2025-02-25

    申请号：US18090810

    申请日：2022-12-29

    Applicant: INTEL CORPORATION

    Inventor： Karthik Vaidyanathan ,  Michael Apodaca ,  Thomas Raoux ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Joshua Barczak

    IPC: G06T15/06 ,  G06F9/30 ,  G06F9/38 ,  G06T1/60 ,  G06T5/70 ,  G06T9/00

    Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

    Apparatus and method for acceleration data structure refit
    7.
    发明授权
    Apparatus and method for acceleration data structure refit 有权

    公开(公告)号：US12229870B2

    公开(公告)日：2025-02-18

    申请号：US17982766

    申请日：2022-11-08

    Applicant: INTEL CORPORATION

    Inventor： Michael Apodaca ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Timothy Rowley ,  Joshua Barczak ,  Travis Schluessler

    IPC: G06T15/06 ,  G06F7/14 ,  G06F9/38 ,  G06F16/901 ,  G06N3/02 ,  G06T1/20 ,  G06T1/60 ,  G06T5/70

    Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

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