公开(公告)号：US11605565B2

公开(公告)日：2023-03-14

申请号：US16236156

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Aaron Lilak ,  Kimin Jun ,  Brennen Mueller ,  Ehren Mannebach ,  Anh Phan ,  Patrick Morrow ,  Hui Jae Yoo ,  Jack T. Kavalieros

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11574910B2

公开(公告)日：2023-02-07

申请号：US16457677

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Willy Rachmady ,  Van H. Le ,  Travis W. Lajoie ,  Urusa Alaan ,  Hui Jae Yoo ,  Sean Ma ,  Aaron Lilak

IPC: H01L27/108 ,  H01L21/764 ,  H01L27/12

Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors. The device also includes one or more air-gaps surrounded by the first dielectric layer and the second dielectric layer on respective adjacent sides of the adjacent capacitors, the top portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors, and the bottom portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors.

公开(公告)号：US11569126B2

公开(公告)日：2023-01-31

申请号：US17061062

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11522012B2

公开(公告)日：2022-12-06

申请号：US16147091

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Ravi Pillarisetty ,  Sasikanth Manipatruni ,  Gregory Chen ,  Hui Jae Yoo ,  Van H. Le ,  Abhishek Sharma ,  Raghavan Kumar ,  Huichu Liu ,  Phil Knag ,  Huseyin Sumbul

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L29/51

Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

公开(公告)号：US20220139823A1

公开(公告)日：2022-05-05

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20220102268A1

公开(公告)日：2022-03-31

申请号：US17033375

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Urusa Alaan ,  Kevin L. Lin ,  Miriam Reshotko ,  Sarah Atanasov ,  Christopher Jezewski ,  Carl Naylor ,  Mauro Kobrinsky ,  Hui Jae Yoo

IPC: H01L23/522 ,  H01L21/768

Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.

公开(公告)号：US11251076B2

公开(公告)日：2022-02-15

申请号：US16940004

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/76 ,  H01L23/52 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US11152254B2

公开(公告)日：2021-10-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Sudipto Naskar ,  Stephanie A. Bojarski ,  Kevin Lin ,  Marie Krysak ,  Tristan A. Tronic ,  Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Jessica M. Torres

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US20200219970A1

公开(公告)日：2020-07-09

申请号：US16240156

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US10438844B2

公开(公告)日：2019-10-08

申请号：US15926870

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/76 ,  H01L23/52 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.