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公开(公告)号：US20210035254A1
公开(公告)日：2021-02-04
申请号：US16924895
申请日：2020-07-09
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
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公开(公告)号：US10379611B2
公开(公告)日：2019-08-13
申请号：US15268494
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Robert M. Toth , Ingo Wald , Aditya S. Yanamandra , Brent E. Insko , Michael Apodaca , Prasoonkumar Surti
Abstract: A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.
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公开(公告)号：US20190197657A1
公开(公告)日：2019-06-27
申请号：US16293044
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
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公开(公告)号：US10282890B2
公开(公告)日：2019-05-07
申请号：US15280912
申请日：2016-09-29
Applicant: Intel Corporation
Inventor： Ingo Wald
IPC: G06T15/06 , G06T1/20 , G06T1/60 , G06F12/0875
Abstract: An apparatus and method are described for performing a distance test in a ray tracing system. For example, one embodiment of a graphics processing apparatus comprises: a ray tracing traversal/intersection unit to identify two or more ray-surface intersections, each of the ray-surface intersections being assigned a unique hit point identifier (ID); and a distance testing module to disambiguate the order of the ray-surface intersections using the hit point ID if the two or more of the ray-surface intersections share the same distance.
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公开(公告)号：US10249073B2
公开(公告)日：2019-04-02
申请号：US14805367
申请日：2015-07-21
Applicant: Intel Corporation
Inventor： Ingo Wald , Gregory P. Johnson
Abstract: Embodiments provide for a graphics processing apparatus comprising multiple compute nodes coupled to a communication layer, a rendering system executing on the multiple compute nodes, wherein the communication layer enables a distributed object executing on one of the multiple compute nodes to communicate with the rendering system, and a distributed framebuffer logic to subdivide a logical screen space for a frame into multiple regions and subdivide ownership of the regions among the multiple compute nodes.
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Patent Agency Ranking
公开(公告)号：US12067641B2
公开(公告)日：2024-08-20
申请号：US17749266
申请日：2022-05-20
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06T1/20 , G06F9/3009 , G06F9/30185 , G06F9/3851 , G06F9/461 , G06F9/4843
Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.
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公开(公告)号：US11935178B2
公开(公告)日：2024-03-19
申请号：US18165842
申请日：2023-02-07
Applicant: Intel Corporation
Inventor： Ingo Wald
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005
Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.
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公开(公告)号：US11776196B2
公开(公告)日：2023-10-03
申请号：US17868610
申请日：2022-07-19
Applicant: INTEL CORPORATION
Inventor： Sven Woop , Attila Afra , Carsten Benthin , Ingo Wald , Johannes Guenther
CPC classification number: G06T15/005 , G06T1/20 , G06T15/06 , G06T17/00 , G09G2360/00
Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US11580686B2
公开(公告)日：2023-02-14
申请号：US17381029
申请日：2021-07-20
Applicant: Intel Corporation
Inventor： Ingo Wald
Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.
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公开(公告)号：US20220277413A1
公开(公告)日：2022-09-01
申请号：US17749275
申请日：2022-05-20
Applicant: Intel Corporation
Inventor： Altug Koker , Ingo Wald , David Puffer , Subramaniam M. Maiyuran , Prasoonkumar Surti , Balaji Vembu , Guei-Yuan Lueh , Murali Ramadoss , Abhishek R. Appu , Joydeep Ray
Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.
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