公开(公告)号：US20220366634A1

公开(公告)日：2022-11-17

申请号：US17746691

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US11341709B2

公开(公告)日：2022-05-24

申请号：US16585880

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US11335035B2

公开(公告)日：2022-05-17

申请号：US17003040

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Carson Brownlee ,  Carsten Benthin ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Prasoonkumar Surti ,  Thomas Raoux

IPC: G06T15/50 ,  G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US11004252B2

公开(公告)日：2021-05-11

申请号：US16236245

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Gabor Liktor ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux

IPC: G06T15/06 ,  G06T15/80 ,  G06T15/04

Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.

公开(公告)号：US10699475B1

公开(公告)日：2020-06-30

申请号：US16235517

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux ,  Carson Brownlee ,  Gabor Liktor

IPC: G06T15/40 ,  G06T15/04 ,  G06T15/00 ,  G06T15/06

Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.