公开(公告)号：US11080046B2

公开(公告)日：2021-08-03

申请号：US17169232

申请日：2021-02-05

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/302 ,  G06F7/483 ,  G06N3/04 ,  G06F17/16 ,  G06F9/30 ,  G09G5/393 ,  G06F7/544 ,  G06F9/38 ,  G06N3/08 ,  G06N3/063 ,  G06N20/00 ,  G06T15/00

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

公开(公告)号：US10943325B2

公开(公告)日：2021-03-09

申请号：US16930841

申请日：2020-07-16

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06F17/16 ,  G06T1/20 ,  G06F9/30 ,  G06T1/60 ,  G06K9/62 ,  G06F12/0888 ,  G06F12/0815 ,  H03M7/30 ,  G06F9/48 ,  G06T15/00 ,  G06N3/04 ,  G06F9/38 ,  G06F12/0831 ,  G06F12/0811 ,  G06N3/08 ,  G06N20/00

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

公开(公告)号：US20210064111A1

公开(公告)日：2021-03-04

申请号：US16994073

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20210035257A1

公开(公告)日：2021-02-04

申请号：US16985329

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US10817012B2

公开(公告)日：2020-10-27

申请号：US16527165

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC: G06F1/06 ,  G06F1/08 ,  H03K19/09 ,  G06F9/38 ,  G06F13/16 ,  H03K19/096 ,  G06T1/60 ,  G06F9/30 ,  G06F1/14

Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US10587244B2

公开(公告)日：2020-03-10

申请号：US16180604

申请日：2018-11-05

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Anupama A. Thaploo ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: H03K19/21 ,  H03K3/012 ,  H03K3/356

Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

公开(公告)号：US10579121B2

公开(公告)日：2020-03-03

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F15/16 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200019401A1

公开(公告)日：2020-01-16

申请号：US16444188

申请日：2019-06-18

Applicant: Intel Corporation

Inventor： Feng Chen ,  Narayan Srinivasa ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Prasoonkumar Surti ,  Ben J. Ashbaugh ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F9/50

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

公开(公告)号：US10417731B2

公开(公告)日：2019-09-17

申请号：US15494886

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F8/41

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

公开(公告)号：US20190243764A1

公开(公告)日：2019-08-08

申请号：US16277267

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N20/00 ,  G06T1/20 ,  G06N3/08

CPC classification number: G06F12/0837 ,  G06F12/0815 ,  G06F2212/62 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06N3/088 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.