公开(公告)号：US11874715B2

公开(公告)日：2024-01-16

申请号：US17966151

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/00 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206

CPC classification number: G06F1/28 ,  G06F1/3203 ,  G06F1/3206

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US10747286B2

公开(公告)日：2020-08-18

申请号：US16004647

申请日：2018-06-11

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20190377395A1

公开(公告)日：2019-12-12

申请号：US16004647

申请日：2018-06-11

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Embodiments are generally directed to dynamic power budget allocation in a multi-processor system. An embodiment of an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20210064111A1

公开(公告)日：2021-03-04

申请号：US16994073

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20190204894A1

公开(公告)日：2019-07-04

申请号：US15859598

申请日：2017-12-31

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Altug Koker ,  Yoav Harel ,  Kenneth Brand ,  Chandra Gurram ,  Eric Finley ,  Bhushan Borole ,  Carlos Nava Rodriguez

IPC: G06F1/32

CPC classification number: G06F1/324

Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.

公开(公告)号：US11493974B2

公开(公告)日：2022-11-08

申请号：US16994073

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/00 ,  G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US10410699B1

公开(公告)日：2019-09-10

申请号：US16024441

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan Borole ,  Muhammad M. Khellah ,  Pascal A. Meinerzhagen

IPC: G11C7/22 ,  G01R31/3185

Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

公开(公告)号：US20230030396A1

公开(公告)日：2023-02-02

申请号：US17966151

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US10983581B2

公开(公告)日：2021-04-20

申请号：US15859598

申请日：2017-12-31

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Altug Koker ,  Yoav Harel ,  Kenneth Brand ,  Chandra Gurram ,  Eric Finley ,  Bhushan Borole ,  Carlos Nava Rodriguez

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3212 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.

公开(公告)号：US10062429B1

公开(公告)日：2018-08-28

申请号：US15488681

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Bhushan Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C5/05 ,  G11C11/4094 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G06F13/40 ,  G06F9/38

CPC classification number: G11C11/4094 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/4068 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.