公开(公告)号：US20230260075A1

公开(公告)日：2023-08-17

申请号：US18305904

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.

公开(公告)号：US11616968B2

公开(公告)日：2023-03-28

申请号：US17094742

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Zhipin Deng ,  Iole Moccagatta ,  Lidong Xu ,  Wenhao Zhang ,  Yi-Jen Chiu

IPC: H04N19/51 ,  G06T7/238 ,  H04N19/57 ,  H04N19/176 ,  H04N19/593

Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.

公开(公告)号：US20220020226A1

公开(公告)日：2022-01-20

申请号：US17388946

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Ke Chen ,  Zhipin Deng ,  Xiaoxia Cai ,  Chen Wang ,  Ya-Ti Peng ,  Yi-Jen Chiu ,  Lidong Xu

IPC: G06T19/20 ,  G06T7/90 ,  G06K9/00 ,  G06T5/00 ,  G06T15/00

Abstract: Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.

公开(公告)号：US20200314447A1

公开(公告)日：2020-10-01

申请号：US16651641

申请日：2017-12-29

Applicant: INTEL CORPORATION

Inventor： Srinivas Embar Raghukrishnan ,  James M. Holland ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Dmitry E. Ryzhov ,  Jason Tanner ,  Lidong Xu ,  Wenhao Zhang

IPC: H04N19/577 ,  H04N19/567 ,  H04N19/513

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

公开(公告)号：US10764592B2

公开(公告)日：2020-09-01

申请号：US13996577

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Lidong Xu ,  Yu Han ,  Zhipin Deng ,  Xiaoxia Cai

IPC: H04N11/04 ,  H04N19/187 ,  H04N19/463 ,  H04N19/61 ,  H04N19/30 ,  H04N19/103 ,  H04N19/117 ,  H04N19/147 ,  H04N19/176 ,  H04N19/50 ,  H04N19/59

Abstract: Systems, devices and methods are described including performing scalable video coding using inter-layer residual prediction. Inter-layer residual prediction in an enhancement layer coding unit, prediction unit, or transform unit may use residual data obtained from a base layer or from a lower enhancement layer. The residual may be subjected to upsample filtering and/or refinement filtering. The upsample or refinement filter coefficients may be predetermined or may be adoptively determined.

公开(公告)号：US10462467B2

公开(公告)日：2019-10-29

申请号：US15433851

申请日：2017-02-15

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Lidong Xu ,  Zhipin Deng ,  Yu Han ,  Xiaoxia Cai ,  Hong Jiang

IPC: H04N19/159 ,  H04N19/503 ,  H04N19/61 ,  H04N19/117 ,  H04N19/33 ,  H04N19/59 ,  H04N19/105 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/184

Abstract: Techniques involving inter layer prediction of scalable video coding are described. Such techniques may employ refining filters.

公开(公告)号：US10291925B2

公开(公告)日：2019-05-14

申请号：US15663134

申请日：2017-07-28

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557 ,  H04N19/625

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.

公开(公告)号：US10075709B2

公开(公告)日：2018-09-11

申请号：US14244364

申请日：2014-04-03

Applicant: Intel Corporation

Inventor： Lidong Xu ,  Yi-Jen Chiu ,  Yu Han ,  Wenhao Zhang

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/61 ,  H04N19/105 ,  H04N19/186 ,  H04N19/159 ,  H04N19/176 ,  H04N19/117

CPC classification number: H04N19/105 ,  H04N19/117 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/61

Abstract: Systems, apparatus and methods are described including determining a prediction residual for a channel of video data; and determining, using the first channel's prediction residual, a prediction residual for a second channel of the video data. Further, a prediction residual for a third channel of the video data may be determined using the second channel's prediction residual.

公开(公告)号：US20180234701A1

公开(公告)日：2018-08-16

申请号：US15950838

申请日：2018-04-11

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Pieter Kapsenberg ,  Lidong Xu ,  Yu Han ,  Zhipin Apple Deng ,  Xiaoxia Cai

IPC: H04N19/60 ,  H04N19/122 ,  H04N19/91 ,  H04N19/96

CPC classification number: H04N19/60 ,  H04N19/122 ,  H04N19/91 ,  H04N19/96

Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation.

公开(公告)号：US09955179B2

公开(公告)日：2018-04-24

申请号：US14737437

申请日：2015-06-11

Applicant: Intel Corporation

Inventor： Yi-Jen Chiu ,  Lidong Xu ,  Hong Jiang

IPC: H04N7/26 ,  H04N19/52 ,  H04N19/577 ,  H04N19/56 ,  H04N19/51 ,  H04N19/44

CPC classification number: H04N19/52 ,  H04N19/44 ,  H04N19/51 ,  H04N19/56 ,  H04N19/577

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.