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    ELECTRICAL INTERCONNECT BRIDGE
    21.
    发明申请
    ELECTRICAL INTERCONNECT BRIDGE 审中-公开
    电气连接桥

    公开(公告)号：WO2017172281A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/020986

    申请日：2017-03-06

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

    IPC: H01L21/48 ,  H01L23/538

    Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

    Abstract translation: 公开了电互连桥技术。 电互连桥可以包括由模制复合材料形成的桥基板。 电互连桥还可以包括桥衬底内的多个布线层，每个布线层具有多个细线和空间（FLS）迹线。 另外，电互连桥可以包括延伸穿过衬底的通孔并且将一个布线层中的至少一个FLS迹线电耦合到另一个布线层中的至少一个FLS迹线。

    SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
    22.
    发明申请
    SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES 审中-公开
    高密度互连结构的表面结构

    公开(公告)号：WO2017172204A2

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/020163

    申请日：2017-03-01

    Applicant: INTEL CORPORATION

    Inventor： UNRUH, David ,  PIETAMBARAM, Srinivas V.

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/60

    Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

    Abstract translation: 示出了无电镀镍，化学镀钯，无电镀锡叠层和相关方法。 形成焊料凸块的示例方法可以包括在阻焊层中的沟槽的基底处在第一材料上形成第二材料层。 第一种材料包括镍，第二种材料包括钯。 该方法进一步包括使用无电沉积工艺在第二材料上沉积包括锡的第三材料，并且使用回流和回流工艺从第三材料形成焊料凸点。

    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER
    24.
    发明申请
    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER 审中-公开

    公开(公告)号：WO2018217188A1

    公开(公告)日：2018-11-29

    申请号：PCT/US2017/033897

    申请日：2017-05-23

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  UNRUH, David ,  TRUONG, Frank ,  LEE, Kyu Oh ,  ZHAO, Junnan ,  CHAVALI, Sri Chaitra Jyotsna

    IPC: H01L23/13 ,  H01L23/14

    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

    SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE CONTAINING NON-HOMOGENEOUS DIELECTRIC LAYER
    25.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE CONTAINING NON-HOMOGENEOUS DIELECTRIC LAYER 审中-公开

    公开(公告)号：WO2018125164A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/069314

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： UNRUH, JR., David Allen ,  PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

    IPC: H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31

    Abstract: Semiconductor packages including package substrates having non-homogeneous dielectric layers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package substrate includes a dielectric layer having a resin-rich region, e.g., a resin-rich sublayer, and a filler-rich region, e.g., a filler-rich sublayer. The sublayers may contain respective mixtures of an organic resin material and an inorganic filler material. The filler-rich sublayer may have a higher density of the inorganic filler material than the resin-rich sublayer. A density of the inorganic filler material may be lesser near a top surface of the dielectric layer in which an electrical interconnect is embedded. The electrical interconnect may have a greater adhesion affinity to the organic resin material than the inorganic filler material, and thus, the electrical interconnect may readily attach to the functionally-graded dielectric layer.

    PACKAGE WITH PASSIVATED INTERCONNECTS
    26.
    发明申请
    PACKAGE WITH PASSIVATED INTERCONNECTS 审中-公开
    包装与被钝化的相互连接

    公开(公告)号：WO2018013311A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2017/038656

    申请日：2017-06-22

    Applicant: INTEL CORPORATION

    Inventor： BOYAPATI, Sri Ranga Sai ,  MANEPALLI, Rahul N. ,  SENEVIRATNE, Dilan ,  PIETAMBARAM, Srinivas V. ,  DARMAWIKARTA, Kristof ,  MAY, Robert Alan ,  SALAMA, Islam A.

    IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065

    Abstract: The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

    Abstract translation: 钝化层可以是可以覆盖半导体封装中的互连层的构建介电层和金属迹线的任何合适的介电材料。 可以在增层介质中形成通孔，并且可以从通孔的底部去除钝化层。 通过去除通孔底部的钝化层，还可以从通孔底部去除任何残留的积累电介质。 因此去除残余积层电介质可能不需要否则会使金属和/或电介质表面变粗糙的去污处理。 通过使用钝化层实现的更平滑的金属和/或电介质表面可以允许更大的工艺宽容度和/或灵活性来制造相对较小的尺寸互连特征和/或相对提高的信号频率和完整性。

    SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
    27.
    发明申请
    SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES 审中-公开

    公开(公告)号：WO2017172204A3

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/020163

    申请日：2017-03-01

    Applicant: INTEL CORPORATION

    Inventor： UNRUH, David ,  PIETAMBARAM, Srinivas V.

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/60

    Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

    STRETCHABLE ELECTRONIC ASSEMBLY
    28.
    发明申请
    STRETCHABLE ELECTRONIC ASSEMBLY 审中-公开
    可伸缩的电子组装

    公开(公告)号：WO2017112342A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2016/063784

    申请日：2016-11-25

    Applicant: INTEL CORPORATION

    Inventor： ALEKSOV, Aleksandar ,  PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L25/075 ,  H01L25/11 ,  H01L25/00

    CPC classification number: H05K1/189 ,  H01L2224/73204 ,  H05K1/0283 ,  H05K2201/09263 ,  H05K2203/1316 ,  H05K2203/308

    Abstract: A stretchable electronic assembly comprising a stretchable body, a plurality of electronic components encapsulated in the stretchable body, at least one meandering conductor connected to at least one electronic component of the plurality of electronic components, at least one hollow pocket formed in the stretchable body, the at least one meandering conductor encapsulated in the stretchable body and the at least one meandering conductor located within the at least one hollow pocket formed in the stretchable body.

    Abstract translation: 一种可拉伸电子组件，包括：可拉伸体，封装在所述可拉伸体中的多个电子部件，连接到所述多个电子部件中的至少一个电子部件的至少一个曲折导体，至少一个 形成在所述伸缩体中的中空袋，所述至少一个蜿蜒导体封装在所述伸缩体中，并且所述至少一个蜿蜒导体位于形成在所述伸缩体中的所述至少一个中空袋内。

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