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    PACKAGE WITH PASSIVATED INTERCONNECTS
    4.
    发明申请
    PACKAGE WITH PASSIVATED INTERCONNECTS 审中-公开
    包装与被钝化的相互连接

    公开(公告)号：WO2018013311A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2017/038656

    申请日：2017-06-22

    Applicant: INTEL CORPORATION

    Inventor： BOYAPATI, Sri Ranga Sai ,  MANEPALLI, Rahul N. ,  SENEVIRATNE, Dilan ,  PIETAMBARAM, Srinivas V. ,  DARMAWIKARTA, Kristof ,  MAY, Robert Alan ,  SALAMA, Islam A.

    IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065

    Abstract: The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

    Abstract translation: 钝化层可以是可以覆盖半导体封装中的互连层的构建介电层和金属迹线的任何合适的介电材料。 可以在增层介质中形成通孔，并且可以从通孔的底部去除钝化层。 通过去除通孔底部的钝化层，还可以从通孔底部去除任何残留的积累电介质。 因此去除残余积层电介质可能不需要否则会使金属和/或电介质表面变粗糙的去污处理。 通过使用钝化层实现的更平滑的金属和/或电介质表面可以允许更大的工艺宽容度和/或灵活性来制造相对较小的尺寸互连特征和/或相对提高的信号频率和完整性。

    HYBRID-CORE THROUGH HOLES AND VIAS
    5.
    发明申请
    HYBRID-CORE THROUGH HOLES AND VIAS 审中-公开
    通过孔和VIAS的混合核心

    公开(公告)号：WO2012078335A2

    公开(公告)日：2012-06-14

    申请号：PCT/US2011/061239

    申请日：2011-11-17

    Applicant: INTEL CORPORATION ,  ROY, Mihir K. ,  SALAMA, Islam A. ,  LI, Yonggang

    Inventor： ROY, Mihir K. ,  SALAMA, Islam A. ,  LI, Yonggang

    IPC: H05K3/46 ,  H05K3/40 ,  H01L23/12 ,  H01L23/045 ,  H01L23/055

    CPC classification number: H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

    Abstract translation: 半导体器件衬底包括布置在第一芯的前表面和后表面上的层压芯的前部和后部。 第一个铁芯有一个镀有金属的圆柱形电镀通孔，并填充有空芯材料。 前部和后部有激光钻孔的锥形过孔，充满导电材料并与镀通孔相连。 后部包括一个与前部连通的整体感应线圈。 第一个核心和叠层核心形成一个带有整体电感线圈的混合核心半导体器件衬底。

    THROUGH MOLD VIA POLYMER BLOCK PACKAGE
    6.
    发明申请
    THROUGH MOLD VIA POLYMER BLOCK PACKAGE 审中-公开
    通过聚合物块包装通过模具

    公开(公告)号：WO2011087573A2

    公开(公告)日：2011-07-21

    申请号：PCT/US2010/057436

    申请日：2010-11-19

    Applicant: INTEL CORPORATION ,  ROY, Mihir K. ,  SALAMA, Islam A. ,  GURUMURTHY, Charavana K. ,  SANKMAN, Robert L.

    Inventor： ROY, Mihir K. ,  SALAMA, Islam A. ,  GURUMURTHY, Charavana K. ,  SANKMAN, Robert L.

    CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.

    Abstract translation: 描述了用于在聚合物块中形成具有贯通模通孔的集成电路芯片封装的方法，并且描述了这种封装。 例如，第一互连层可以形成在模制聚合物块上，其中第一互连层包括穿过第一聚合物层并连接到块的第一互连。 然后，可以在第一互连层上形成至少一个第二互连层，其中第二互连层包括穿过第二聚合物层并且连接到第一互连层的第一互连的第二互连。 然后可以通过模块形成模制过孔，进入第一互连层以及第一互连。 贯穿模具通孔可以填充有焊料以形成接触第一互连并在块体上方延伸的凸块。 其他实施例也被描述和要求保护。

    METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE
    7.
    发明申请
    METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE 审中-公开

    公开(公告)号：WO2009042741A3

    公开(公告)日：2009-04-02

    申请号：PCT/US2008/077612

    申请日：2008-09-25

    Applicant: INTEL CORPORATION ,  BCHIR, Omar J. ,  JOMAA, Houssam ,  SALAMA, Islam A. ,  LI, Yonggang

    Inventor： BCHIR, Omar J. ,  JOMAA, Houssam ,  SALAMA, Islam A. ,  LI, Yonggang

    IPC: H01L21/306 ,  H01L21/304

    Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.

    SYSTEMS AND METHODS FOR SEMICONDUCTOR PACKAGES USING PHOTOIMAGEABLE LAYERS
    8.
    发明申请
    SYSTEMS AND METHODS FOR SEMICONDUCTOR PACKAGES USING PHOTOIMAGEABLE LAYERS 审中-公开
    用于光电图层的半导体封装的系统和方法

    公开(公告)号：WO2018013121A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2016/042285

    申请日：2016-07-14

    Applicant: INTEL CORPORATION

    Inventor： CHAVALI, Sri Chaitra ,  ALUR, Siddharth K. ,  SCHUCKMAN, Amanda E. ,  ALUR, Amruthavalli Pallavi ,  SALAMA, Islam A. ,  DENG, Yikang ,  DARMAWIKARTA, Kristof

    IPC: H01L23/00 ,  H01L23/12

    Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

    Abstract translation: 本发明的各种实施例涉及半导体封装和用于制造半导体封装的方法。 此外，本文公开了涉及使用具有与模具材料的机械特性基本相似的机械特性的可光成像电介质（PID）层的系统和方法。 例如，本公开可以用于用于晶片/面板级重新分布层（RDL）和/或扇出（fan-out）封装应用的无凸起无激光器嵌入式衬底结构（BLESS）技术的背景下。 所公开的实施例可以减少在用于半导体封装的各种处理步骤期间对多个干抗蚀剂膜（DFR）层压步骤的需要，并且由于薄PID材料的可用性也可以促进多层计数。

    METHODS OF FORMING SENSOR INTEGRATED PACKAGES AND STRUCTURES FORMED THEREBY
    10.
    发明申请
    METHODS OF FORMING SENSOR INTEGRATED PACKAGES AND STRUCTURES FORMED THEREBY 审中-公开
    形成传感器集成包和其结构的方法

    公开(公告)号：WO2016160189A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/019574

    申请日：2016-02-25

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kyu Oh ,  ZHOU, Zheng ,  SALAMA, Islam A. ,  EID, Feras ,  OSTER, Sasha N. ,  KONG, Lay Wai ,  SOTO GONZALEZ, Javier

    IPC: B81B7/02

    CPC classification number: B81B7/0077 ,  B81C2203/0109

    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

    Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

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