公开(公告)号：US12100623B2

公开(公告)日：2024-09-24

申请号：US17848191

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US12009433B2

公开(公告)日：2024-06-11

申请号：US16001837

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Van H. Le ,  Inanc Meric ,  Gilbert Dewey ,  Sean Ma ,  Abhishek A. Sharma ,  Miriam Reshotko ,  Shriram Shivaraman ,  Kent Millard ,  Matthew V. Metz ,  Wilhelm Melitz ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78678 ,  H01L21/28194 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/7869

Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

公开(公告)号：US20230114214A1

公开(公告)日：2023-04-13

申请号：US17485158

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Stephen Cea ,  Biswajeet Guha ,  Leonard Guler ,  Tahir Ghani ,  Sean Ma

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

公开(公告)号：US11527612B2

公开(公告)日：2022-12-13

申请号：US16146778

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax M. Crum ,  Sean Ma ,  Tahir Ghani ,  Susmita Ghose ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/683

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220336284A1

公开(公告)日：2022-10-20

申请号：US17848191

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US11335789B2

公开(公告)日：2022-05-17

申请号：US16142045

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Cory Weber ,  Van H. Le ,  Sean Ma

IPC: H01L29/47 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/108 ,  H01L27/24 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

公开(公告)号：US11257904B2

公开(公告)日：2022-02-22

申请号：US16024706

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20200044095A1

公开(公告)日：2020-02-06

申请号：US16490503

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).