公开(公告)号：US20240219632A1

公开(公告)日：2024-07-04

申请号：US18091535

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Umesh Prasad ,  Suddhasattwa Nad ,  Benjamin T. Duong ,  Yi Yang

IPC: G02B6/122 ,  G02B1/02 ,  G02B3/00

CPC classification number: G02B6/122 ,  G02B1/02 ,  G02B3/0087 ,  G02B2006/12061

Abstract: Technologies for integrated graded index (GRIN) lenses for photonic circuits is disclosed. In one illustrative embodiment, a glass substrate has a cavity in which a GRIN lens is disposed. In other embodiments, the GRIN lens may be on a surface of the glass substrate. The GRIN lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. Another component such as a photonic integrated circuit (PIC) die may also have a GRIN lens and focus the free-space beam into a waveguide in the PIC die. The use of GRIN lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.

公开(公告)号：US20240186264A1

公开(公告)日：2024-06-06

申请号：US18061083

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Yi Yang ,  Eungnak Han ,  Suddhasattwa Nad ,  Marcel A. Wall

IPC: H01L23/00 ,  B32B17/10 ,  C09D201/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/562 ,  B32B17/10 ,  C09D201/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2270/00 ,  B32B2307/732 ,  B32B2457/08

Abstract: In one embodiment, an apparatus includes a glass substrate, a metal, and a polymeric layer between the metal and the glass substrate. The polymeric layer includes polymer molecules with an R1 group, an R2 group, a polymer backbone between the R1 group and R2 group, and an R3 group side-attached to the polymer backbone. The polymeric layer is bonded to the glass substrate via the R1 groups and bonded to the metal via the R2 groups.

公开(公告)号：US20240113048A1

公开(公告)日：2024-04-04

申请号：US17957590

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Benjamin Duong ,  Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Brandon C. Marin ,  Gang Duan ,  Yi Yang

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/647 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US11869171B2

公开(公告)日：2024-01-09

申请号：US17090170

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Xiaoming Chen ,  Junjie Huang ,  Tao Lv ,  Yuanke Luo ,  Yi Yang ,  Feng Chen ,  Zhiming Wang ,  Zhiqiao Zheng ,  Shandong Wang

IPC: G06T5/00 ,  G06N3/04

CPC classification number: G06T5/002 ,  G06N3/04 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

公开(公告)号：US20230420389A1

公开(公告)日：2023-12-28

申请号：US17847652

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Yi Yang ,  Srinivas Pietambaram ,  Suddhasattwa Nad

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894

Abstract: An electronic device package comprises a conductive feature over a first surface of a package substrate, the conductive feature to couple to an integrated circuit die; a first dielectric layer on the conductive feature, the first dielectric layer having a first thickness and comprising silicon and nitrogen; a second dielectric layer over the first dielectric layer and having a second thickness different than the first thickness and comprising silicon and nitrogen; and a third dielectric layer over the second dielectric layer and comprising an organic material.

公开(公告)号：US20230420346A1

公开(公告)日：2023-12-28

申请号：US17846303

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Yi Yang ,  Suddhasattwa Nad ,  Ali Lehaf ,  Jason Steill

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/4853

Abstract: Various embodiments disclosed relate to a semiconductor assembly interconnect structure. The present disclosure includes an interconnect structure that case include a substrate, a metallic layer thereon, an adhesion promoter film formed over the metallic layer and forming a flat region over a flat portion of the metallic layer, a solder resist layer formed over the adhesion promoter film, an opening in the solder resist layer and the adhesion promoter film in the flat region of the adhesion promotion film, the opening connecting to the flat portion of the metallic layer, and a stacked electrical connector formed on the metallic layer within the opening. Methods of making an interconnect structure can include patterning a metallic layer on a substrate, depositing an adhesion promoter layer on the metallic layer opposite the substrate, patterning the adhesion promoter layer to expose selected portions of the metallic layer, and depositing a surface finish layer on the exposed selected portions of the metallic layer.

公开(公告)号：US20230395467A1

公开(公告)日：2023-12-07

申请号：US17833648

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01L23/481 ,  H01L23/49822 ,  H01L23/49816 ,  H01L21/486 ,  H01L21/76898 ,  H05K1/112 ,  H01L24/16 ,  H05K3/429 ,  H05K3/4644 ,  H05K1/0306 ,  H01L2224/16225

Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.