公开(公告)号：US20240186136A1

公开(公告)日：2024-06-06

申请号：US18061126

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Whitney M. Bryks ,  Shayan Kaviani ,  Joshua J. Stacey ,  Thomas S. Heaton

IPC: H01L21/02 ,  C23C16/02

CPC classification number: H01L21/0212 ,  C23C16/0209 ,  C23C16/0272 ,  H01L21/02422 ,  H01L21/0262

Abstract: In one embodiment, an integrated circuit apparatus (e.g., package substrate) includes a polymeric layer between a metal and a dielectric or between a metal and a glass. The polymeric layer may be conformally deposited using a vacuum-based vapor deposition technique, e.g., initiated chemical vapor deposition (iCVD).

公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US20240096561A1

公开(公告)日：2024-03-21

申请号：US17948586

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Benjamin Duong ,  Shayan Kaviani ,  Joshua Stacey ,  Miranda Ngan ,  Dilan Seneviratne ,  Thomas Heaton ,  Srinivas Venkata Ramanuja Pietambaram ,  Whitney Bryks ,  Jieying Kong

IPC: H01G4/33 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01L28/92 ,  H01L25/16

Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.

公开(公告)号：US20250006781A1

公开(公告)日：2025-01-02

申请号：US18344695

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Darko Grujicic ,  Marcel Wall ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01G4/012 ,  H01L21/48 ,  H01L23/498

Abstract: Carbon nanofiber capacitor apparatus and related methods are disclosed herein. An example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. The capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.

公开(公告)号：US20230298971A1

公开(公告)日：2023-09-21

申请号：US17699031

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Shayan Kaviani ,  Darko Grujicic ,  Suddhasattwa Nad ,  Miranda Ngan

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/145 ,  H01L21/486 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/16145

Abstract: A microelectronic structure and a method of forming same. The microelectronic structure includes: a core substrate including one of a glass material or an organic material, and defining a plurality of trenches therein; electrically conductive vias extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including: a trench liner adjacent walls of a corresponding one of the plurality of trenches, the trench liner including an electrically conductive polymer material having double carbon bonds; and a metal structure on the trench liner.

公开(公告)号：US20250132239A1

公开(公告)日：2025-04-24

申请号：US19005161

申请日：2024-12-30

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Thomas Stanley Heaton ,  Shayan Kaviani ,  Yonggang Li ,  Mahdi Mohammadighaleni ,  Bai Nie ,  Dilan Seneviratne ,  Joshua James Stacey ,  Hiroki Tanaka ,  Elham Tavakoli ,  Ehsan Zamani

IPC: H01L23/498

Abstract: Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.

公开(公告)号：US20240113048A1

公开(公告)日：2024-04-04

申请号：US17957590

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Benjamin Duong ,  Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Brandon C. Marin ,  Gang Duan ,  Yi Yang

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/647 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240107784A1

公开(公告)日：2024-03-28

申请号：US17954917

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Shayan Kaviani ,  Benjamin Duong ,  Miranda Ngan ,  Mahdi Mohammadighaleni

IPC: H01L51/44

CPC classification number: H01L51/448

Abstract: Methods, apparatus, systems, and articles of manufacture utilizing conjugated polymers in integrated circuit packages with glass substrates are disclosed. A disclosed integrated circuit (IC) package includes: a glass substrate; a first electrode; an organic material; and a second electrode. The first electrode is between the glass substrate and the organic material. The organic material includes at least one of a conjugated polymer or a metal-organic supramolecule. The organic material is between the first electrode and the second electrode.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC: H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US20240113046A1

公开(公告)日：2024-04-04

申请号：US17957257

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Benjamin Duong ,  Srinivasan Raman ,  Yi Yang

IPC: H01L23/62 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/62 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/24 ,  H01L2224/24145 ,  H01L2924/12036

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.