公开(公告)号：US20160268397A1

公开(公告)日：2016-09-15

申请号：US15160525

申请日：2016-05-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L21/76

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

公开(公告)号：US09349834B2

公开(公告)日：2016-05-24

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US09275895B2

公开(公告)日：2016-03-01

申请号：US14166090

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC: H01L21/763 ,  H01L21/768 ,  H01L21/762 ,  H01L27/105 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.

Abstract translation: 一种制造具有半导体本体的半导体部件的方法，包括提供第一导电型的基板。 在基板上设置第二导电类型的掩埋半导体层。 功能单元半导体层设置在掩埋半导体层上。 至少一个到达衬底的沟槽形成在半导体本体中。 形成绝缘层，其覆盖沟槽的内壁，并使沟槽内部与功能单元半导体层和埋入半导体层电绝缘，绝缘层在沟槽底部的区域中具有至少一个开口。 所述至少一个沟槽填充有第一导电类型的导电半导体材料，其中所述导电半导体材料形成从所述半导体主体的表面到所述衬底的电接触。

公开(公告)号：US09269592B2

公开(公告)日：2016-02-23

申请号：US14464849

申请日：2014-08-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

IPC: H01L21/383 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

Abstract: A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

Abstract translation: 晶体管通过在半导体衬底中形成包括第一脊部分和第二脊部分的脊而形成，所述脊部沿着第一方向延伸，形成源极区域，漏极区域，沟道区域，漏极延伸区域和 栅极与沟道区相邻，在脊中，掺杂具有第一导电类型的掺杂剂的沟道区，并用第二导电类型的掺杂剂掺杂源区和漏区。 形成漏极延伸区域包括在第二脊部中形成掺杂有第一导电类型的芯部分，并且形成漏极延伸区域还包括形成掺杂有第二导电类型的覆盖部分，盖部分形成为 邻近第二脊部分的至少一个或两个侧壁。

公开(公告)号：US20160035654A1

公开(公告)日：2016-02-04

申请号：US14614119

申请日：2015-02-04

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Andreas Meiser

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L23/49562 ,  H01L21/4807 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0603 ,  H01L2224/08245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0532 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

公开(公告)号：US20150311317A1

公开(公告)日：2015-10-29

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US20150311196A1

公开(公告)日：2015-10-29

申请号：US14795207

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Andreas Meiser ,  Steffen Thiele

IPC: H01L27/06 ,  H03K19/0185 ,  H01L29/78 ,  H01L27/088 ,  H01L29/739 ,  H01L29/10 ,  H01L23/528 ,  H03K17/687 ,  H01L23/48

CPC classification number: H01L27/0623 ,  H01L23/481 ,  H01L23/528 ,  H01L27/0826 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/7327 ,  H01L29/735 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L2924/0002 ,  H03K17/687 ,  H03K19/018507 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081 ,  H01L2924/00

Abstract: An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first surface with a normal direction defining a vertical direction, an opposite surface, a first area including a vertical power field-effect transistor structure, a second area including a three-terminal step-down level-shifter, and a third area including a three-terminal step-up level-shifter. A terminal of the vertical power field-effect transistor structure is electrically connected with one of the three-terminal step-down level-shifter and the three-terminal step-up level-shifter.

Abstract translation: 提供集成半导体器件。 根据实施例，集成半导体器件包括半导体本体，其具有限定垂直方向的法线方向的第一表面，相对表面，包括垂直功率场效应晶体管结构的第一区域， 端子降压电平转换器和包括三端子升压电平转换器的第三区域。 垂直功率场效应晶体管结构的端子与三端降压电平转换器和三端升压电平转换器中的一个电连接。

公开(公告)号：US20150279978A1

公开(公告)日：2015-10-01

申请号：US14673072

申请日：2015-03-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/735 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/785 ,  H01L29/808

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a body region, and a gate electrode structure adjacent to the body region. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The body region is disposed between the source region and the drain region. The body region includes an upper body region at the main surface and a lower body region remote from the main surface. A first width of the lower body region is smaller than a second width of the upper body region. The first width and the second width are measured in a direction perpendicular to the first direction.

Abstract translation: 半导体器件包括具有主表面的半导体衬底中的晶体管。 晶体管包括源区域，漏极区域，体区域和与身体区域相邻的栅电极结构。 源极区域和漏极区域沿着第一方向设置，第一方向平行于主表面。 体区设置在源区和漏区之间。 主体区域包括在主表面处的上体区域和远离主表面的下身体区域。 下体区域的第一宽度小于上体区域的第二宽度。 第一宽度和第二宽度在垂直于第一方向的方向上测量。

公开(公告)号：US20150137224A1

公开(公告)日：2015-05-21

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体本体中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，电连接到源极区的源极接触，电连接到漏极区的漏极接触，以及沟道区处的栅电极。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 通道区域具有沿着第一方向延伸的第一脊的形状。 源极接触和漏极接触中的一个与第一主表面相邻，源极接触和漏极接触中的另一个与与第一主表面相对的第二主表面相邻。

公开(公告)号：US20150102404A1

公开(公告)日：2015-04-16

申请号：US14053633

申请日：2013-10-15

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region.

Abstract translation: 半导体器件包括形成在包括主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区和栅电极。 源极区域和漏极区域沿着第一方向设置，第一方向平行于主表面。 沟道区具有沿着第一方向延伸的脊的形状，脊包括顶侧和第一和第二侧壁。 栅电极设置在沟道区的第一侧壁处，栅电极不存在于沟道区的第二侧壁。