公开(公告)号：US20230361087A1

公开(公告)日：2023-11-09

申请号：US17736519

申请日：2022-05-04

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Baessler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/4952 ,  H01L23/3121

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

公开(公告)号：US11621204B2

公开(公告)日：2023-04-04

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US10211133B2

公开(公告)日：2019-02-19

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US20180138111A1

公开(公告)日：2018-05-17

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/83906 ,  H01L2924/014

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US20180040537A1

公开(公告)日：2018-02-08

申请号：US15665574

申请日：2017-08-01

Applicant: Infineon Technologies AG

Inventor： Andreas GRASSMANN ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

IPC: H01L23/473 ,  H01L21/56 ,  H01L23/433 ,  H01L21/48 ,  B60R16/02 ,  H01L23/31

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

公开(公告)号：US09496228B2

公开(公告)日：2016-11-15

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。

公开(公告)号：US20140353818A1

公开(公告)日：2014-12-04

申请号：US13909133

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Ottmar GEITNER ,  Wolfram HABLE ,  Andreas Grassmann ,  Frank Winter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/89 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/26135 ,  H01L2224/29005 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/30181 ,  H01L2224/83048 ,  H01L2224/83139 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/97 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer

Abstract translation: 提供一种制造包括两个基板的功率模块的方法，其中所述方法包括在第一基板之上设置第一厚度的补偿层; 在补偿层之上设置第二衬底; 以及在所述第二衬底设置在所述补偿层上之后，将所述补偿层的厚度从所述第一厚度减小到第二厚度

公开(公告)号：US12300643B2

公开(公告)日：2025-05-13

申请号：US17537822

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Adrian Lis ,  Peter Scherl ,  Achim Althaus

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

公开(公告)号：US11901273B2

公开(公告)日：2024-02-13

申请号：US17385731

申请日：2021-07-26

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Peter Luniewski

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01R12/58

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3171 ,  H01L23/49833 ,  H01L23/49844 ,  H01R12/585 ,  H01L23/49861

Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

公开(公告)号：US11682611B2

公开(公告)日：2023-06-20

申请号：US16907734

申请日：2020-06-22

Applicant: Infineon Technologies AG

Inventor： Michael Niendorf ,  Ludwig Busch ,  Oliver Markus Kreiter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/4952 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2924/1203 ,  H01L2924/13055

Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.