公开(公告)号：US20240162129A1

公开(公告)日：2024-05-16

申请号：US18504309

申请日：2023-11-08

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer ,  Michael Fügl ,  Frank Singer ,  Thorsten Meyer ,  Fabian Craes ,  Andreas Grassmann ,  Frederik Otto

IPC: H01L23/498 ,  B82Y10/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/07

CPC classification number: H01L23/49811 ,  B82Y10/00 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49844 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181

Abstract: A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.

公开(公告)号：US11502042B2

公开(公告)日：2022-11-15

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US11302668B2

公开(公告)日：2022-04-12

申请号：US16720867

申请日：2019-12-19

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss ,  Peter Scherl

IPC: H01L21/677 ,  H01L21/56 ,  H01L21/67 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

公开(公告)号：US20210166998A1

公开(公告)日：2021-06-03

申请号：US17176576

申请日：2021-02-16

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10886186B2

公开(公告)日：2021-01-05

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/08 ,  H01L23/00 ,  H01L23/40

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US20190259688A1

公开(公告)日：2019-08-22

申请号：US16280181

申请日：2019-02-20

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Thorsten Meyer

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.

公开(公告)号：US10217695B2

公开(公告)日：2019-02-26

申请号：US15367920

申请日：2016-12-02

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Klaus Pressel ,  Maciej Wojnowski

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.

公开(公告)号：US20170309582A1

公开(公告)日：2017-10-26

申请号：US15496477

申请日：2017-04-25

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Walter Hartner ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01Q1/22 ,  H01L29/06

CPC classification number: H01L23/66 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01Q1/2283 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.

公开(公告)号：US20170283247A1

公开(公告)日：2017-10-05

申请号：US15090010

申请日：2016-04-04

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Dominic Maier ,  Johannes Lodermeyer ,  Bernd Stadler

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0051 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/095 ,  B81B2207/096 ,  B81C1/00238 ,  B81C1/00325 ,  B81C2203/0145 ,  H01L2224/16225 ,  H01L2924/19105

Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, a lid, and an integrated circuit die. The lid is over the MEMS die and defines a cavity between the lid and the MEMS die. The integrated circuit die is attached to an inner side of the lid. The integrated circuit die is electrically coupled to the MEMS die.

公开(公告)号：US09711621B2

公开(公告)日：2017-07-18

申请号：US14446741

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.