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公开(公告)号：US10549985B2
公开(公告)日：2020-02-04
申请号：US15692938
申请日：2017-08-31
Applicant: Infineon Technologies AG
Inventor： Dominic Maier , Matthias Steiert , Chau Fatt Chiang , Christian Geissler , Bernd Goller , Thomas Kilger , Johannes Lodermeyer , Franz-Xaver Muehlbauer , Chee Yang Ng , Beng Keh See , Claus Waechter
Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
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公开(公告)号：US10539779B2
公开(公告)日：2020-01-21
申请号：US15674149
申请日：2017-08-10
Applicant: Infineon Technologies AG
Inventor： Ludwig Heitzer , Derek Debie , Klaus Elian , Cyrus Ghahremani , Johannes Lodermeyer , Oskar Neuhoff , Johann Strasser
Abstract: A microelectromechanical systems (MEMS) package assembly and a method of manufacturing the same is provided. The MEMS package assembly includes a substrate, a housing coupled to the substrate to form a cavity, wherein the housing includes a transparent plate disposed above and parallel to the substrate and is configured to permit a transmission of light therethrough, and a MEMS chip disposed within the cavity and including a first main surface proximal to the transparent plate and a second main surface opposite to the first main surface and coupled to the substrate. The MEMS chip is oriented such that the first main surface is tilted at a tilt angle with respect to the transparent plate.
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3.发明申请公开(公告)号：US20150155271A1
公开(公告)日：2015-06-04
申请号：US14617797
申请日：2015-02-09
Applicant: Infineon Technologies AG
Inventor： Ralf Otremba , Josef Hoeglauer , Joachim Mahler , Johannes Lodermeyer
IPC: H01L25/00 , H01L21/768 , H01L25/07
CPC classification number: H01L25/50 , H01L21/4857 , H01L21/568 , H01L21/76897 , H01L23/3107 , H01L23/492 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/071 , H01L25/072 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/12105 , H01L2224/131 , H01L2224/1411 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24011 , H01L2224/2402 , H01L2224/24105 , H01L2224/24135 , H01L2224/245 , H01L2224/40105 , H01L2224/40227 , H01L2224/73209 , H01L2224/73267 , H01L2224/82106 , H01L2224/96 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2224/84 , H01L2924/00012 , H01L2924/01029 , H01L2924/00 , H01L2924/014 , H01L2224/05552
Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
Abstract translation: 一种器件包括具有第一接触焊盘的第一功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 该器件还包括具有第一接触焊盘的第二功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 第一功率半导体芯片和第二功率半导体芯片彼此重叠配置，第一功率半导体芯片的第一面朝向第二功率半导体芯片的第一面的方向。 此外，第一功率半导体芯片至少部分地位于第二功率半导体芯片的轮廓外侧。
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公开(公告)号：US11387533B2
公开(公告)日：2022-07-12
申请号：US16032589
申请日：2018-07-11
Applicant: Infineon Technologies AG
Inventor： Maciej Wojnowski , Dirk Hammerschmidt , Walter Hartner , Johannes Lodermeyer , Chiara Mariotti , Thorsten Meyer
Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.
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公开(公告)号：US20190103378A1
公开(公告)日：2019-04-04
申请号：US16148316
申请日：2018-10-01
Applicant: Infineon Technologies AG
Inventor： Irmgard Escher-Poeppel , Khalil Hosseini , Johannes Lodermeyer , Joachim Mahler , Thorsten Meyer , Georg Meyer-Berg , Ivan Nikitin , Reinhard Pufall , Edmund Riedl , Klaus Schmidt , Manfred Schneegans , Patrick Schwarz
IPC: H01L23/00
Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
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Patent Agency Ranking
公开(公告)号：US10571682B2
公开(公告)日：2020-02-25
申请号：US15674149
申请日：2017-08-10
Applicant: Infineon Technologies AG
Inventor： Ludwig Heitzer , Derek Debie , Klaus Elian , Cyrus Ghahremani , Johannes Lodermeyer , Oskar Neuhoff , Johann Strasser
Abstract: A microelectromechanical systems (MEMS) package assembly and a method of manufacturing the same is provided. The MEMS package assembly includes a substrate, a housing coupled to the substrate to form a cavity, wherein the housing includes a transparent plate disposed above and parallel to the substrate and is configured to permit a transmission of light therethrough, and a MEMS chip disposed within the cavity and including a first main surface proximal to the transparent plate and a second main surface opposite to the first main surface and coupled to the substrate. The MEMS chip is oriented such that the first main surface is tilted at a tilt angle with respect to the transparent plate.
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7.发明申请公开(公告)号：US20180148322A1
公开(公告)日：2018-05-31
申请号：US15692938
申请日：2017-08-31
Applicant: Infineon Technologies AG
Inventor： Dominic Maier , Matthias Steiert , Chau Fatt Chiang , Christian Geissler , Bernd Goller , Thomas Kilger , Johannes Lodermeyer , Franz-Xaver Muehlbauer , Chee Yang Ng , Beng Keh See , Claus Waechter
Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
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公开(公告)号：US20170283247A1
公开(公告)日：2017-10-05
申请号：US15090010
申请日：2016-04-04
Applicant: Infineon Technologies AG
Inventor： Thorsten Meyer , Dominic Maier , Johannes Lodermeyer , Bernd Stadler
CPC classification number: B81B7/0051 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81B2207/095 , B81B2207/096 , B81C1/00238 , B81C1/00325 , B81C2203/0145 , H01L2224/16225 , H01L2924/19105
Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, a lid, and an integrated circuit die. The lid is over the MEMS die and defines a cavity between the lid and the MEMS die. The integrated circuit die is attached to an inner side of the lid. The integrated circuit die is electrically coupled to the MEMS die.
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公开(公告)号：US10923364B2
公开(公告)日：2021-02-16
申请号：US16118651
申请日：2018-08-31
Applicant: Infineon Technologies AG
Inventor： Kristina Mayer , Michael Ledutke , Johannes Lodermeyer
Abstract: A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier; filling a cavity with a molding material; pressing the semiconductor chips arranged on the carrier into the molding material; and separating the molding material with the semiconductor chips embedded therein from the carrier, wherein main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material.
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公开(公告)号：US10734352B2
公开(公告)日：2020-08-04
申请号：US16148316
申请日：2018-10-01
Applicant: Infineon Technologies AG
Inventor： Irmgard Escher-Poeppel , Khalil Hosseini , Johannes Lodermeyer , Joachim Mahler , Thorsten Meyer , Georg Meyer-Berg , Ivan Nikitin , Reinhard Pufall , Edmund Riedl , Klaus Schmidt , Manfred Schneegans , Patrick Schwarz
IPC: H01L23/00
Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
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