公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11843054B2

公开(公告)日：2023-12-12

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Miriam Reshotko ,  Matthew Metz ,  Yih Wang ,  Gilbert Dewey ,  Jack Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Abhishek Sharma ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L23/5226 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78645 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11812599B2

公开(公告)日：2023-11-07

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

IPC: G11C8/00 ,  H10B12/00 ,  H01L27/12 ,  G11C11/4096

CPC classification number: H10B12/00 ,  G11C11/4096 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1266

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US11727260B2

公开(公告)日：2023-08-15

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22 ,  G06N3/065 ,  H10B10/00 ,  H10B12/00 ,  H10B53/00

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/54 ,  H10B10/18 ,  H10B12/01 ,  H10B12/033 ,  H10B12/20 ,  H10B12/50 ,  H10B53/00 ,  G11C11/221 ,  G11C11/409 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US11659722B2

公开(公告)日：2023-05-23

申请号：US16226209

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah Karpov ,  Brian Doyle ,  Anup Pancholi ,  Abhishek Sharma

IPC: H10K19/20 ,  H01L27/12 ,  H01L27/28 ,  H01L29/66 ,  H01L29/786 ,  H01L51/05 ,  H01L51/10

CPC classification number: H01L27/286 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/283 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0558 ,  H01L51/102

Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

公开(公告)号：US11631717B2

公开(公告)日：2023-04-18

申请号：US16147068

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Charles Kuo ,  Prashant Majhi ,  Abhishek Sharma ,  Willy Rachmady

IPC: H01L27/24 ,  G11C7/18 ,  G11C8/14 ,  G11C13/00 ,  H01L45/00

Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

公开(公告)号：US11569238B2

公开(公告)日：2023-01-31

申请号：US16222940

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Kimin Jun ,  Hui Jae Yoo ,  Patrick Morrow ,  Sean T. Ma ,  Ahn Phan ,  Abhishek Sharma ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L23/528 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/417 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11462568B2

公开(公告)日：2022-10-04

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Justin Weber ,  Harold Kennel ,  Willy Rachmady ,  Gilbert Dewey ,  Van H. Le ,  Abhishek Sharma ,  Patrick Morrow ,  Ashish Agrawal

IPC: H01L27/12 ,  H01L21/8256 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11444205B2

公开(公告)日：2022-09-13

申请号：US16143001

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew Metz ,  Benjamin Chu-Kung ,  Abhishek Sharma ,  Van H. Le ,  Miriam R. Reshotko ,  Christopher J. Jezewski ,  Ryan Arch ,  Ande Kitamura ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Lawrence Wong ,  Tahir Ghani

IPC: H01L29/786 ,  H01L23/31 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/24 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US11417770B2

公开(公告)日：2022-08-16

申请号：US16142075

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Nazila Haratipour ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Shriram Shivaraman ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Arnab Sen Gupta

IPC: H01L29/786 ,  H01L29/49 ,  H01L27/108 ,  H01L29/66 ,  H01L27/24

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.