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公开(公告)号:US20220407212A1
公开(公告)日:2022-12-22
申请号:US17350184
申请日:2021-06-17
Applicant: Intel Corporation
Inventor: Neelam PRABHU GAUNKAR , Georgios C. DOGIAMIS , Telesphor KAMGAING , Veronica STRONG , Aleksandar ALEKSOV
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related creating millimeter wave components within a glass core of a substrate within a semiconductor package. These millimeter wave components, which include resonators, isolators, directional couplers, and circulators, may be combined to form other structures such as filters or multiplexers. Other embodiments may be described and/or claimed.
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公开(公告)号:US20220406698A1
公开(公告)日:2022-12-22
申请号:US17350818
申请日:2021-06-17
Applicant: Intel Corporation
Inventor: Aleksandar ALEKSOV , Neelam PRABHU GAUNKAR , Georgios C. DOGIAMIS , Telesphor KAMGAING , Veronica STRONG , Johanna M. SWAN
IPC: H01L23/498 , H01L23/58 , H01L21/48 , H01F27/28
Abstract: Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.
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公开(公告)号:US20220102261A1
公开(公告)日:2022-03-31
申请号:US17544693
申请日:2021-12-07
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Mathew J. MANUSHAROW , Krishna BHARATH , William J. LAMBERT , Robert L. SANKMAN , Aleksandar ALEKSOV , Brandon M. RAWLINGS , Feras EID , Javier SOTO GONZALEZ , Meizi JIAO , Suddhasattwa NAD , Telesphor KAMGAING
IPC: H01L23/498 , H01F17/00 , H01F27/40 , H01L49/02 , H01F27/28 , H01F41/04 , H01G4/33 , H01L21/48 , H01L23/66
Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
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公开(公告)号:US20200235449A1
公开(公告)日:2020-07-23
申请号:US16841072
申请日:2020-04-06
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Mathew MANUSHAROW , Krishna BHARATH , Zhichao ZHANG , Yidnekachew S. MEKONNEN , Aleksandar ALEKSOV , Henning BRAUNISCH , Feras EID , Javier SOTO
Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
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公开(公告)号:US20200219814A1
公开(公告)日:2020-07-09
申请号:US16648640
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Veronica STRONG , Aleksandar ALEKSOV , Brandon RAWLINGS
IPC: H01L23/538 , H01L23/522 , H01L23/00
Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.
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26.
公开(公告)号:US20200052404A1
公开(公告)日:2020-02-13
申请号:US16345171
申请日:2016-12-14
Applicant: Intel Corporation
Inventor: Feras EID , Sasha N. OSTER , Telesphor KAMGAING , Georgios C. DOGIAMIS , Aleksandar ALEKSOV
IPC: H01Q9/04 , H01L23/552 , H01L21/56 , H01L23/31 , H01L23/66 , H01L23/495 , H01Q1/24 , H01Q1/52 , H01Q1/22 , H01Q19/22
Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
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公开(公告)号:US20190036002A1
公开(公告)日:2019-01-31
申请号:US16072166
申请日:2016-04-01
Applicant: Intel Corporation
Inventor: Shawna M. LIFF , Feras EID , Aleksandar ALEKSOV , Sasha N. OSTER , Baris BICEN , Thomas L. SOUNART , Johanna M. SWAN , Adel A. ELSHERBINI , Valluri R. RAO
Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.
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公开(公告)号:US20190033500A1
公开(公告)日:2019-01-31
申请号:US16072173
申请日:2016-04-01
Applicant: Intel Corporation
Inventor: Thomas L. SOUNART , Baris BICEN , Feras EID , Sasha N. OSTER , Aleksandar ALEKSOV , Shawna M. LIFF , Valluri R. RAO , Johanna M. SWAN
Abstract: Embodiments of the invention include an optical grating switch integrated into an organic substrate and methods of forming such devices. According to an embodiment, the optical grating switch may include a cavity formed into an organic substrate. Additionally, the optical grating switch may include an array of moveable beams anchored to the organic substrate and suspended over the cavity. In an embodiment of the invention, each of the moveable beams in the optical grating switch may include a piezoelectric region formed over end portions of the moveable beam and a top electrode formed over a top surface of each of the piezoelectric regions. In order to reflect or diffract light, embodiments of the invention may include moveable beams that include a reflective surface formed over a central portion of the moveable beam.
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公开(公告)号:US20180226310A1
公开(公告)日:2018-08-09
申请号:US15748138
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: Feras EID , Adel A. ELSHERBINI , Henning BRAUNISCH , Yidnekachew MEKONNEN , Krishna BHARATH , Mathew J. MANUSHAROW , Aleksandar ALEKSOV , Nathan FRITZ
IPC: H01L23/14 , H01L21/48 , H01L23/473 , H01L23/538 , H01L23/492
CPC classification number: H01L23/147 , H01L21/486 , H01L21/4871 , H01L23/12 , H01L23/473 , H01L23/492 , H01L23/5389
Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.
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公开(公告)号:US20180145031A1
公开(公告)日:2018-05-24
申请号:US15876080
申请日:2018-01-19
Applicant: Intel Corporation
Inventor: Henning BRAUNISCH , Chia-Pin CHIU , Aleksandar ALEKSOV , Hinmeng AU , Stefanie M. LOTZ , Johanna M. SWAN , Sujit SHARAN
IPC: H01L23/538 , H01L23/13 , H01L23/00 , H01L25/065 , H01L21/683
Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
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