公开(公告)号：US20250006841A1

公开(公告)日：2025-01-02

申请号：US18345127

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Rachel A. Steinhardt ,  Punyashloka Debashis ,  Kevin P. O'Brien ,  Matthew V. Metz ,  Scott B. Clendenning ,  Brandon Holybee ,  Marko Radosavljevic ,  Ian Alexander Young ,  I-Cheng Tung ,  Sudarat Lee ,  Raseong Kim ,  Pratyush P. Buragohain

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/221 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US12119387B2

公开(公告)日：2024-10-15

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Nazila Haratipour ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Jitendra Kumar Jha ,  Matthew V. Metz ,  Mengcheng Lu ,  Anand S. Murthy ,  Koustav Ganguly ,  Ryan Keech ,  Glenn A. Glass ,  Arnab Sen Gupta

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20240234579A1

公开(公告)日：2024-07-11

申请号：US18444520

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20240006488A1

公开(公告)日：2024-01-04

申请号：US17856620

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  David Kohen ,  Natalie Briggs ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L21/0332

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11444205B2

公开(公告)日：2022-09-13

申请号：US16143001

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew Metz ,  Benjamin Chu-Kung ,  Abhishek Sharma ,  Van H. Le ,  Miriam R. Reshotko ,  Christopher J. Jezewski ,  Ryan Arch ,  Ande Kitamura ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Lawrence Wong ,  Tahir Ghani

IPC: H01L29/786 ,  H01L23/31 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/24 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US11417770B2

公开(公告)日：2022-08-16

申请号：US16142075

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Nazila Haratipour ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Shriram Shivaraman ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Arnab Sen Gupta

IPC: H01L29/786 ,  H01L29/49 ,  H01L27/108 ,  H01L29/66 ,  H01L27/24

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.

公开(公告)号：US20210375873A1

公开(公告)日：2021-12-02

申请号：US16888910

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H. Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC: H01L27/108 ,  H01L25/065

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US12224309B2

公开(公告)日：2025-02-11

申请号：US17116315

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC: H01L23/522 ,  H01L49/02

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.