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    Interface discovery between partitions of a programmable logic device
    23.
    发明授权
    Interface discovery between partitions of a programmable logic device 有权

    公开(公告)号：US11301415B2

    公开(公告)日：2022-04-12

    申请号：US15862249

    申请日：2018-01-04

    Applicant: Intel Corporation

    Inventor： Evan Custodio

    IPC: H03K19/17756 ,  G06F15/78 ,  H03K19/0175 ,  H03K19/17736 ,  G06F30/34

    Abstract: Systems, methods, and devices for enhancing the flexibility of an integrated circuit device with partially reconfigurable regions are provided. For example, a discovery interface may determine and/or communicate a suitable logical protocol interface to control data transfer between regions on the integrated circuit device. The techniques provided herein result in more flexible partial reconfiguration options to enable greater compatibility between accelerator hosts and accelerator function units.

    Technologies for providing function as service tiered scheduling and mapping for multi-operator architectures
    25.
    发明授权
    Technologies for providing function as service tiered scheduling and mapping for multi-operator architectures 有权

    公开(公告)号：US11218538B2

    公开(公告)日：2022-01-04

    申请号：US16234865

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Ned Smith ,  Evan Custodio ,  Suraj Prabhkaran ,  Ignacio Astilleros Diez

    IPC: H04L12/927 ,  H04L29/08 ,  H04L12/24 ,  H04L12/14 ,  H04M15/00

    Abstract: Technologies for determining a set of edge resources to offload a workload from a client compute device based on a brokering logic provided by a service provider include a device that includes circuitry that is in communication with edge resources. The circuitry is to receive a brokering logic from a service provider receive a request from a client compute device, wherein the request includes a function to be used to execute the request and one or more parameters associated with the client compute device, determine the one or more parameters, select, as a function of the one or more parameters and the brokering logic, a physical implementation to perform the function, wherein the physical implementation indicates a set of edge resources and a performance level for each edge resource of the set of edge resources, and perform, in response to a selection of the physical implementation, the request using the set of edge resources associated with the physical implementation.

    Technologies for remote networked accelerators
    26.
    发明授权
    Technologies for remote networked accelerators 有权

    公开(公告)号：US10970246B2

    公开(公告)日：2021-04-06

    申请号：US16402507

    申请日：2019-05-03

    Applicant: Intel Corporation

    Inventor： Paul H. Dormitzer ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio

    IPC: G06F15/16 ,  G06F15/173 ,  G06F13/42

    Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.

    TECHNOLOGIES FOR COMPRESSING COMMUNICATION FOR ACCELERATOR DEVICES
    27.
    发明申请
    TECHNOLOGIES FOR COMPRESSING COMMUNICATION FOR ACCELERATOR DEVICES 审中-公开

    公开(公告)号：US20200348854A1

    公开(公告)日：2020-11-05

    申请号：US16398948

    申请日：2019-04-30

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat

    IPC: G06F3/06

    Abstract: Technologies for compressing communications for accelerator devices are disclosed. An accelerator device may include a communication abstraction logic units to manage communication with one or more remote accelerator devices. The communication abstraction logic unit may receive communication to and from a kernel on the accelerator device. The communication abstraction logic unit may compress and decompress the communication without instruction from the corresponding kernel. The communication abstraction logic unit may choose when and how to compress communications based on telemetry of the accelerator device and the remote accelerator device.

    TECHNOLOGIES FOR ESTABLISHING COMMUNICATION CHANNEL BETWEEN ACCELERATOR DEVICE KERNELS
    29.
    发明申请
    TECHNOLOGIES FOR ESTABLISHING COMMUNICATION CHANNEL BETWEEN ACCELERATOR DEVICE KERNELS 审中-公开

    公开(公告)号：US20200004712A1

    公开(公告)日：2020-01-02

    申请号：US16236255

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat ,  Sujoy Sen ,  Slawomir Putyrski ,  Paul Dormitzer ,  Joseph Grecco

    IPC: G06F13/40 ,  G06F13/36

    Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

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