公开(公告)号：US11374004B2

公开(公告)日：2022-06-28

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Stephen M. Cea ,  Sayed Hasan ,  Kerryann M. Foley ,  Patrick Morrow ,  Colin D. Landon ,  Ehren Mannebach

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US11367789B2

公开(公告)日：2022-06-21

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Sean T. Ma ,  Harold Kennel

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/778 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US11328988B2

公开(公告)日：2022-05-10

申请号：US16728887

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L27/12 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11296087B2

公开(公告)日：2022-04-05

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L29/49 ,  H01L27/108 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US11276755B2

公开(公告)日：2022-03-15

申请号：US16303654

申请日：2016-06-17

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L21/70 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US11276694B2

公开(公告)日：2022-03-15

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/207

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US11251227B2

公开(公告)日：2022-02-15

申请号：US16480598

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L27/22 ,  H01L27/24 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L43/12 ,  H01L45/00

Abstract: A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.

公开(公告)号：US11239232B2

公开(公告)日：2022-02-01

申请号：US16017971

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Rishabh Mehandru

IPC: H01L21/82 ,  H01L27/02 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20210399113A1

公开(公告)日：2021-12-23

申请号：US17465652

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Prashant Majhi ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/22 ,  H01L27/24 ,  H01L29/40 ,  H01L29/49

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

公开(公告)号：US11183594B2

公开(公告)日：2021-11-23

申请号：US15938153

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L27/108 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H01L21/311

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.