公开(公告)号：US11443885B2

公开(公告)日：2022-09-13

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Sandeep Gaan ,  Sri Ranga Sai Boyapati ,  Prithwish Chatterjee ,  Sameer Paital ,  Rahul Jain ,  Junnan Zhao

IPC: H01F17/00 ,  H01F17/06 ,  H01F41/04 ,  H01F27/28 ,  H01F27/24

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US20220230800A1

公开(公告)日：2022-07-21

申请号：US17713662

申请日：2022-04-05

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11322290B2

公开(公告)日：2022-05-03

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20200251467A1

公开(公告)日：2020-08-06

申请号：US16855376

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20200212020A1

公开(公告)日：2020-07-02

申请号：US16234302

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/528 ,  H01L23/498 ,  H01L21/56

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20200066543A1

公开(公告)日：2020-02-27

申请号：US16113109

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

公开(公告)号：US20200006210A1

公开(公告)日：2020-01-02

申请号：US16019807

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer.

公开(公告)号：US20190206780A1

公开(公告)日：2019-07-04

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US11894282B2

公开(公告)日：2024-02-06

申请号：US16446538

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Sergio Antonio Chan Arguedas ,  Peng Li ,  Chandra Mohan Jha ,  Aravindha R. Antoniswamy ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang

IPC: H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/053

CPC classification number: H01L23/3675 ,  H01L23/053 ,  H01L23/433 ,  H01L23/49816

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

公开(公告)号：US11651885B2

公开(公告)日：2023-05-16

申请号：US16637006

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Ying Wang ,  Cheng Xu ,  Kyu Oh Lee ,  Sheng Li ,  Yikang Deng

IPC: H01F17/00 ,  H01F27/255

CPC classification number: H01F17/0013 ,  H01F27/255 ,  H01F2017/002 ,  H01F2017/0066

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.