公开(公告)号：US20200006631A1

公开(公告)日：2020-01-02

申请号：US16024411

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Justin Brockman ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.

公开(公告)号：US20200006626A1

公开(公告)日：2020-01-02

申请号：US16022094

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Ian Young ,  Kaan Oguz ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford ,  Tanay Gosavi

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

公开(公告)号：US20200006424A1

公开(公告)日：2020-01-02

申请号：US16022564

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Atm G. Sarwar ,  Ian Young ,  Hui Jae Yoo ,  Christopher Weigand ,  Benjamin Buford

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01F41/34

Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.

公开(公告)号：US20190386205A1

公开(公告)日：2019-12-19

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  H01F10/32 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

公开(公告)号：US20250113520A1

公开(公告)日：2025-04-03

申请号：US18375051

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Andrey Vyatskikh ,  Paul Fischer ,  Paul Nordeen ,  Kevin O'Brien ,  Chelsey Dorow ,  Carl H. Naylor ,  Uygar Avci

IPC: H01L29/775 ,  H01L21/762

Abstract: Techniques and mechanisms for a transition metal dichalcogenide (TMD) material to be grown on one structure, and then transferred to a different structure. In an embodiment, one or more monolayers of a TMD material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. A material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. The resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. The ablation enables the substrate to be separated from the one or more monolayers. In an embodiment, a residue on a surface of the one or more TMD monolayers is an artefact of the layer transfer process.

公开(公告)号：US12266712B2

公开(公告)日：2025-04-01

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H10B61/00 ,  H10B63/00 ,  H10N50/85 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：US20230197860A1

公开(公告)日：2023-06-22

申请号：US17560069

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Chelsey Dorow ,  Sudarat Lee ,  Kevin O'Brien ,  Ashish V. Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/4908

Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.

公开(公告)号：US11462678B2

公开(公告)日：2022-10-04

申请号：US16955723

申请日：2018-03-09

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Kaan Oguz ,  Charles Kuo ,  Mark Doczy ,  Noriyuki Sato

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.

公开(公告)号：US11437567B2

公开(公告)日：2022-09-06

申请号：US16348364

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Christopher Wiegand ,  MD Tofizur Rahman ,  Daniel Ouelette ,  Angeline Smith ,  Juan Alzate Vinasco ,  Charles Kuo ,  Mark Doczy ,  Kaan Oguz ,  Kevin O'Brien ,  Brian Doyle ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.