公开(公告)号：US09818751B2

公开(公告)日：2017-11-14

申请号：US15490754

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Kimin Jun ,  Patrick Morrow

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10832 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/20 ,  H01L28/87 ,  H01L28/91 ,  H01L29/945

Abstract: Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

公开(公告)号：US09490201B2

公开(公告)日：2016-11-08

申请号：US13798575

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC: H01L23/522 ,  H01L21/20 ,  H01L23/00 ,  H01L23/535 ,  H01L21/74 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Abstract translation: 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。

公开(公告)号：US12288810B2

公开(公告)日：2025-04-29

申请号：US18415251

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20250006695A1

公开(公告)日：2025-01-02

申请号：US18344260

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Kimin Jun ,  Omkar G. Karhade ,  Mohit Bhatia ,  Nitin A. Deshpande ,  Prashant Majhi ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.

公开(公告)号：US12107060B2

公开(公告)日：2024-10-01

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US20240063202A1

公开(公告)日：2024-02-22

申请号：US17820968

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Thomas Sounart ,  Henning Braunisch ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Kimin Jun ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5223 ,  H01L28/90 ,  H01L24/08 ,  H01L23/49811 ,  H01L23/481 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.

公开(公告)号：US20240063180A1

公开(公告)日：2024-02-22

申请号：US17891654

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel Elsherbini ,  Omkar Karhade ,  Bhaskar Jyoti Krishnatreya ,  Mohammad Enamul Kabir ,  Jiraporn Seangatith ,  Tushar Talukdar ,  Shawna Liff ,  Johanna Swan ,  Feras Eid

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3185 ,  H01L24/05

Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.

公开(公告)号：US20240063071A1

公开(公告)日：2024-02-22

申请号：US17891880

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jeffery Bielefeld ,  Adel Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Gauri Auluck ,  Kimin Jun ,  Mohammad Enamul Kabir ,  Nagatoshi Tsunoda ,  Renata Camillo-Castillo ,  Tristan A. Tronic ,  Xavier Brun

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L25/0655 ,  H01L24/08 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.

公开(公告)号：US20230299040A1

公开(公告)日：2023-09-21

申请号：US17699024

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Jay Prakash Gupta ,  Souvik Ghosh ,  Kimin Jun ,  Bhupendra Kumar ,  Shashi Vyas ,  Anup Pancholi

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03849 ,  H01L2224/08147 ,  H01L2224/05687 ,  H01L2224/05147 ,  H01L2224/05666 ,  H01L2224/05187 ,  H01L2224/8009 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80948 ,  H01L2924/35121

Abstract: A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.