公开(公告)号：US20160173074A1

公开(公告)日：2016-06-16

申请号：US14567987

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03K5/135 ,  G11C8/18

CPC classification number: H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

Abstract translation: 接收包括第一边缘和第二边缘的信号。 信号的第一个边沿与第一个时钟同步，信号的同步的第一个边沿被传递到一个输出端。 同步导致信号的第一个边沿的延迟。 信号的第二个边沿传递给输出。 信号的经过的第二边缘的延迟小于第一时钟的至少一个时钟周期的信号的第一边沿的延迟。

公开(公告)号：US11321263B2

公开(公告)日：2022-05-03

申请号：US14574352

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: H05K7/10 ,  G06F13/40 ,  H04L49/10 ,  H04L12/54

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US20210124579A1

公开(公告)日：2021-04-29

申请号：US17115989

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US10474458B2

公开(公告)日：2019-11-12

申请号：US15787129

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G09G5/00 ,  G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T15/00 ,  G06N20/00

Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

公开(公告)号：US10440377B2

公开(公告)日：2019-10-08

申请号：US13649560

申请日：2012-10-11

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Ram K. Krishnamurthy

IPC: H04N11/02 ,  H04N19/43 ,  H04N19/567

Abstract: In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.

公开(公告)号：US09961019B2

公开(公告)日：2018-05-01

申请号：US14579729

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Yejoong Kim

IPC: H04L12/933

CPC classification number: H04L49/109 ,  H04L45/60 ,  H04L49/60

Abstract: A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.

公开(公告)号：US09787571B2

公开(公告)日：2017-10-10

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/26 ,  H04L12/727 ,  H04L12/933 ,  H04L12/773 ,  G06F15/78

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

公开(公告)号：US09626334B2

公开(公告)日：2017-04-18

申请号：US14582607

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew

IPC: G06K9/62 ,  G06F15/80 ,  G06F7/00 ,  G06F17/30

CPC classification number: G06F15/8092 ,  G06F7/00 ,  G06F17/3033

Abstract: Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.

公开(公告)号：US20160182393A1

公开(公告)日：2016-06-23

申请号：US14579303

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Aaron T. Stillmaker

IPC: H04L12/863 ,  H04L12/935 ,  H04L12/26 ,  H04L12/911

CPC classification number: H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

Abstract translation: 接收到第一分组交换预约请求。 根据尽力而为的通信方案，通过第一电路交换信道来传送与第一分组交换预约请求相关联的数据。 接收第二分组交换预约请求。 根据保证的吞吐量通信方案，通过第二电路交换信道来传送与第二分组交换预约请求相关联的数据。

公开(公告)号：US20160179728A1

公开(公告)日：2016-06-23

申请号：US14574352

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  H04L12/54 ,  H04L49/10

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract translation: 一种装置包括包括输入端口和输出端口的第一端口组。 该装置还包括多个第二端口组。 每个第二端口组包括耦合到第一端口组的输出端口的输入端口和耦合到第一端口组的输入端口的输出端口。 多个第二端口组将以第一最大带宽进行通信，并且第一端口组将以高于第一最大带宽的第二最大带宽进行通信。