Abstract:
Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.
Abstract:
Described is a computing platform, which comprises: a non-volatile memory having a firmware boot program; and a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Measurement (PPM) interface data structures including an error injection table structure to provide error injection services to an OS.
Abstract:
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.
Abstract:
Systems, apparatuses and methods may provide for technology to identify a first set of fault domains associated with data nodes in a data distribution framework and identify a second set of fault domains associated with storage nodes in a data storage framework, wherein the data distribution framework overlays and is different from the data storage framework. Moreover, a mapping data structure may be generated based on the first and second sets of fault domains, wherein the mapping data structure associates data nodes and storage nodes that share fault domains with one another. In one example, the fault domains are storage racks.
Abstract:
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.
Abstract:
Described is a computing platform, which comprises: a non-volatile memory having a firmware boot program; and a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Measurement (PPM) interface data structures including an error injection table structure to provide error injection services to an OS.
Abstract:
An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.