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    Method and apparatus for quick resumption of a processing system with volatile memory
    4.
    发明授权
    Method and apparatus for quick resumption of a processing system with volatile memory 有权
    用于快速恢复具有易失性存储器的处理系统的方法和装置

    公开(公告)号：US08631259B2

    公开(公告)日：2014-01-14

    申请号：US13764245

    申请日：2013-02-11

    Applicant: Intel Corporation

    Inventor： Michael Rothman ,  Glenn Hinton ,  Vincent Zimmer ,  Michael Kinney ,  Mark Doran

    IPC: G06F9/24 ,  G06F15/177

    CPC classification number: G06F1/3234 ,  G06F9/4418

    Abstract: When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

    Abstract translation: 当从睡眠模式转换到活动模式时，处理系统将第一级恢复内容和第二级恢复内容加载到处理系统的易失性存储器中。 第一阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的第一程序的上下文数据。 第二阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的另一程序的上下文数据。 处理系统可以在所有第二阶段恢复内容已经被加载到易失性存储器之前为第一程序提供用户界面。 描述和要求保护其他实施例。

    System and method for supporting metered clients with manycore
    9.
    发明授权
    System and method for supporting metered clients with manycore 有权

    公开(公告)号：US10585702B2

    公开(公告)日：2020-03-10

    申请号：US14171509

    申请日：2014-02-03

    Applicant: Intel Corporation

    Inventor： Vincent J. Zimmer ,  Michael A. Rothman ,  Mark Doran

    IPC: G06F9/46 ,  G06F13/00 ,  G06F15/00 ,  G06F9/50

    Abstract: In some embodiments, the invention involves partitioning resources of a manycore platform for simultaneous use by multiple clients, or adding/reducing capacity to a single client. Cores and resources are activated and assigned to a client environment by reprogramming the cores' route tables and source address decoders. Memory and I/O devices are partitioned and securely assigned to a core and/or a client environment. Instructions regarding allocation or reallocation of resources is received by an out-of-band processor having privileges to reprogram the chipsets and cores. Other embodiments are described and claimed.

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