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    High data rate integrated circuit with transmitter configuration
    21.
    发明授权
    High data rate integrated circuit with transmitter configuration 有权

    公开(公告)号：US11536688B2

    公开(公告)日：2022-12-27

    申请号：US16808276

    申请日：2020-03-03

    Applicant: LIFE TECHNOLOGIES CORPORATION

    Inventor： Keith G. Fife ,  Jungwook Yang

    IPC: G01N27/414 ,  G06F30/392 ,  G06F30/394

    Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

    High data rate integrated circuit with transmitter configuration
    22.
    发明授权
    High data rate integrated circuit with transmitter configuration 有权

    公开(公告)号：US10605767B2

    公开(公告)日：2020-03-31

    申请号：US14971173

    申请日：2015-12-16

    Applicant: LIFE TECHNOLOGIES CORPORATION

    Inventor： Keith G. Fife ,  Jungwook Yang

    IPC: G01N27/414 ,  G06F30/392 ,  G06F30/394

    Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

    Ion-sensing charge-accumulation circuits and methods
    25.
    发明授权
    Ion-sensing charge-accumulation circuits and methods 有权
    离子感应电荷积累电路及方法

    公开(公告)号：US09239313B2

    公开(公告)日：2016-01-19

    申请号：US14477125

    申请日：2014-09-04

    Applicant: LIFE TECHNOLOGIES CORPORATION

    Inventor： Keith G. Fife

    IPC: G01N27/414 ,  G01N27/30

    CPC classification number: G01N27/414 ,  G01N27/302 ,  G01N27/4145 ,  G01N27/4148

    Abstract: An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid. The second charge control electrode can control transmission of the plurality of charge packets out of the gate semiconductor region and into the drain diffusion region in response to a second control signal. The drain diffusion region can receive the plurality of charge packets from the gate semiconductor region via the second electrode semiconductor region.

    Abstract translation: 离子敏感电路可以包括电荷累积装置，以根据流体的离子浓度和至少一个控制和读出晶体管累积多个电荷包，以产生作为累积的函数的输出信号 多个充电分组，输出信号表示溶液的离子浓度。 电荷蓄积装置可以包括在第一电极半导体区域上方的第一电荷控制电极，栅极半导体区域上方的电浮置栅极结构和离子敏感钝化表面以下的第二电荷控制电极，以及在第二电极半导体区域上方的第二电荷控制电极， 漏极扩散区域。 响应于第一控制信号，第一控制电极可以控制电荷进入栅极半导体区域。 离子敏感钝化表面可以被配置为接收流体。 第二充电控制电极可以响应于第二控制信号来控制多个电荷分组从栅极半导体区域的传输并进入漏极扩散区域。 漏极扩散区域可以经由第二电极半导体区域从栅极半导体区域接收多个电荷包。

    HIGH DATA RATE INTEGRATED CIRCUIT WITH TRANSMITTER CONFIGURATION
    26.
    发明申请
    HIGH DATA RATE INTEGRATED CIRCUIT WITH TRANSMITTER CONFIGURATION 有权

    公开(公告)号：US20250164440A1

    公开(公告)日：2025-05-22

    申请号：US18984472

    申请日：2024-12-17

    Applicant: Life Technologies Corporation

    Inventor： Keith G. Fife ,  Jungwook Yang

    IPC: G01N27/414 ,  G06F30/392 ,  G06F30/394

    Abstract: A high data rate integrated circuit, such as an integrated circuit including a large sensor array, may be implemented using clock multipliers in individual power domains, coupled to sets of transmitters, including a transmitter pair configuration. Reference clock distribution circuitry on the integrated circuit distributes a relatively low speed reference clock. In a transmitter pair configuration, each pair comprises a first transmitter and a second transmitter in a transmitter power domain. Also, each pair of transmitters includes a clock multiplier connected to the reference clock distribution circuitry, and disposed between the first and second transmitters, which produces a local transmit clock.

    Column ADC
    27.
    发明授权
    Column ADC 有权

    公开(公告)号：US11307166B2

    公开(公告)日：2022-04-19

    申请号：US16850823

    申请日：2020-04-16

    Applicant: LIFE TECHNOLOGIES CORPORATION

    Inventor： Keith G. Fife

    IPC: G01N27/414 ,  H01L27/146 ,  H04N5/374 ,  G01N33/00 ,  C12Q1/6869 ,  G01J1/46 ,  G01R29/26 ,  H01L29/66

    Abstract: The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a column of chemically-sensitive pixels. Each chemically-sensitive pixel may comprise a chemically-sensitive transistor, and a row selection device. The chemical detection circuit may further comprise a column interface circuit coupled to the column of chemically-sensitive pixels and an analog-to-digital converter (ADC) coupled to the column interface circuit. Each column interface circuit and column-level ADC may be arrayed with other identical circuits and share critical resources such as biasing and voltage references, thereby saving area and power.

    Methods and apparatus for measuring analytes using large scale FET arrays
    30.
    发明授权
    Methods and apparatus for measuring analytes using large scale FET arrays 有权

    公开(公告)号：US10379079B2

    公开(公告)日：2019-08-13

    申请号：US14971435

    申请日：2015-12-16

    Applicant: LIFE TECHNOLOGIES CORPORATION

    Inventor： Keith G. Fife

    IPC: G01N27/414

    Abstract: A semiconductor device, comprising a first field effect transistor (FET) connected in series to a second FET, and a third FET connected in series to the first FET and the second FET. The semiconductor device further includes bias circuitry coupled to the first FET and the second FET, and an output conductor coupled to a terminal of the second FET, wherein the output conductor obtains an output signal from the second FET that is independent of the first FET.

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