公开(公告)号：AU2002361761A1

公开(公告)日：2003-07-24

申请号：AU2002361761

申请日：2002-12-18

Applicant: MICRON TECHNOLOGY INC

Inventor： JOHNSON BRIAN ,  KEETH BRENT ,  JANZEN JEFFREY W ,  MANNING TROY A ,  MARTIN CHRIS G

IPC: G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C29/00

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

公开(公告)号：AU1082099A

公开(公告)日：1999-05-03

申请号：AU1082099

申请日：1998-10-13

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G06F1/12 ,  H04L7/00

Abstract: A coupling circuit for coupling a first signal generated in a first circuit operating in a first clock domain to a second circuit operating in a second clock domain. The coupling circuit includes a first gate for coupling the first signal to a first logic circuit unless the coupling circuit has already applied a signal to the second circuit. The first logic circuit includes a pair of second gates that are enabled by respective rising and falling edges of the first clock signal. Thus, each of the second gates generates an output signal on respective transitions of the first clock signal as long as the first gate is coupling the first signal to the first logic circuit. The first logic circuit also includes a pair of latches coupled to respective outputs of the second gates. Each of the latches is set by its respective second gate generating the output signal. The second logic gates are coupled to a second logic circuit having a pair of third gates that are enabled by respective rising and falling edges of the second clock signal. Thus, each of the second gates generates an output signal on respective transitions of the second clock signal if the latch to which it is connected is generating an output signal. The output signal is also used as the reset signal to disable the first gate and reset the latches. Since the output signal is generated on the first transition of the first clock signal after the first signal is applied to the coupling circuit, the coupling circuit generates a single output signal that is synchronized to the second clock signal.

公开(公告)号：AU8373898A

公开(公告)日：1999-02-08

申请号：AU8373898

申请日：1998-07-02

Applicant: MICRON TECHNOLOGY INC

Inventor： BAKER RUSSEL JACOB ,  MANNING TROY A

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/00

公开(公告)号：AU5963198A

公开(公告)日：1998-08-07

申请号：AU5963198

申请日：1998-01-21

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/401 ,  G11C7/22 ,  G11C11/407 ,  G11C29/12 ,  G11C29/14 ,  G11C29/00 ,  G06F11/24

Abstract: A test circuit provides a test clock signal to a SDRAM of the type having an internal clock input. The test circuit and the SDRAM are housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal, and a test enable terminal adapted to receive a test enable signal. The test circuit includes a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal of the package, and an output coupled to the internal clock input of the SDRAM. The logic circuit couples the clock terminal to the output of the logic circuit in response to the clock enable signal being active and the test enable signal being inactive. The logic circuit derives the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applies the test clock signal to the output of the logic circuit when the test enable signal is active. The test clock signal has a frequency that is greater than the frequencies of the periodic signals.

公开(公告)号：DE69936865T2

公开(公告)日：2008-05-15

申请号：DE69936865

申请日：1999-06-23

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/00 ,  G11C11/407 ,  G06F1/08 ,  G06F1/12 ,  G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

Abstract: A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.

公开(公告)号：DE60224727D1

公开(公告)日：2008-03-06

申请号：DE60224727

申请日：2002-12-18

Applicant: MICRON TECHNOLOGY INC

Inventor： JOHNSON BRIAN ,  KEETH BRENT ,  JANZEN JEFFREY W ,  MANNING TROY A ,  MARTIN CHRIS G

IPC: G01R31/28 ,  G11C7/22 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/14

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

公开(公告)号：AT231647T

公开(公告)日：2003-02-15

申请号：AT98906164

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/407 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C7/00

Abstract: A command generator for a dynamic random access memory decrements a counter from an initial counter value which is a function of the clock speed. The output of the counter is decoded to generate various command signals for the DRAM. In particular, each command signal is generated by a respective counter value, with the correspondency between counter values and command signals being a function of the clock speed. The counter decrements from larger initial values at higher clock speeds, and the command signals are generally issued by the decoder at higher counter values for higher clock speeds. As a result of the lack of correspondency between the timing of the command signals and the number of clock cycles occurring during a memory access, the timing of the command signals may be selected to optimize the speed of the DRAM desired despite substantial variations in clock speed.

公开(公告)号：AT224242T

公开(公告)日：2002-10-15

申请号：AT99911154

申请日：1999-03-05

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G06F11/22 ,  G06F11/00 ,  G11C11/401 ,  G11C29/44 ,  G11C29/50 ,  H01L21/82 ,  B05D1/00

Abstract: A method and circuit for recording the performance parameters in an integrated circuit. A speed grade register is programmed by the manufacturer with an indication of the speed capability of the integrated circuit. The integrated circuit also includes a clock speed register that is programmed by the user with an indication of the frequency of a clock signal that will be used to synchronize the operation of the integrated circuit. The speed grade and clock speed indications are used to select a set of performance data from a performance data register to provide an indication of the performance of the integrated circuit at the indicated speed grade and clock speed.

公开(公告)号：AU2002255686A1

公开(公告)日：2002-09-24

申请号：AU2002255686

申请日：2002-03-12

Applicant: MICRON TECHNOLOGY INC

Inventor： BRENT KEETH ,  MANNING TROY A ,  JANZEN JEFFERY W ,  RYAN KEVIN J ,  JOHNSON BRIAN

IPC: G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G06F13/42 ,  G11C11/4067 ,  G11C11/4076 ,  G11C11/4072 ,  G11C7/20

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

公开(公告)号：AU4711299A

公开(公告)日：2000-01-10

申请号：AU4711299

申请日：1999-06-23

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/407 ,  G06F1/08 ,  G06F1/12 ,  G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

Abstract: A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.