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    System latency levelization for read data
    2.
    发明专利
    System latency levelization for read data 审中-公开
    用于读取数据的系统延迟级别

    公开(公告)号：JP2007272929A

    公开(公告)日：2007-10-18

    申请号：JP2007182589

    申请日：2007-07-11

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー,インコーポレイテッドMicron Technology, Inc.

    Inventor： JANZEN JEFFERY W ,  KEETH BRENT ,  RYAN KEVIN J ,  MANNING TROY A ,  BRIAN JOHNSON

    IPC: G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    CPC classification number: G11C7/22 ,  G11C7/1072

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device equalizing the system read latencies of every memory device in a high speed memory system.
    SOLUTION: In a high speed memory subsystem, differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and a memory controller results in widely varying system read latencies. The differences in system read latencies of each device are thereby compared, and each memory device is operated with a device system read latency which causes every device to exhibit the same system read latency.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在高速存储器系统中均衡每个存储器件的系统读取延迟的存储器件。 解决方案：在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间的差异导致大量变化的系统读延迟。 因此，比较了每个设备的系统读取延迟的差异，并且每个存储器设备以设备系统读取延迟来操作，这导致每个设备呈现相同的系统读取延迟。 版权所有（C）2008，JPO＆INPIT

    Memory device and method having data bus with multiple pre-fetch i/o configuration
    4.
    发明专利
    Memory device and method having data bus with multiple pre-fetch i/o configuration 有权
    具有多个PRE-FETCH I / O配置的数据总线的存储器件和方法

    公开(公告)号：JP2012248267A

    公开(公告)日：2012-12-13

    申请号：JP2012172023

    申请日：2012-08-02

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー, インク.

    Inventor： KEETH BRENT ,  JOHNSON BRAIN ,  MANNING TROY A

    IPC: G11C11/409 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/407

    CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    Abstract: PROBLEM TO BE SOLVED: To provide a memory adaptable to either a memory having high speed narrow data bus width or a memory having low speed wide data bus width.SOLUTION: In either mode of high speed or low speed, 32-bits data from each of two memory arrays are pre-fetched into respective sets of 32 flip-flops 120. In the high speed mode, the pre-fetched data bits are transferred in parallel to four parallel-to-serial converters 150a. The converters transform the parallel data bits to a burst of eight serial data bits and apply the burst to each of four data bus terminals 160. In the low speed mode, two sets of pre-fetched data bits are transferred in parallel to eight parallel-to serial converters. The converters transform the parallel data bits to a burst of eight serial data bits and apply the burst to each of eight data bus terminals.

    Abstract translation: 要解决的问题：提供适用于具有高速窄数据总线宽度的存储器或具有低速宽数据总线宽度的存储器的存储器。 解决方案：在任何一种高速或低速模式下，两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据 位并行传输到四个并行到串行转换器150a。 转换器将并行数据位变换为八个串行数据位的脉冲串，并将该脉冲串应用于四个数据总线端子160中的每一个。在低速模式中，两组预取数据位并行传输到八个并行数据位， 到串行转换器。 转换器将并行数据位转换为八个串行数据位的脉冲串，并将突发应用于八个数据总线端子中的每一个。 版权所有（C）2013，JPO＆INPIT

    Method and apparatus for determining actual write latency and accurately aligning start of data capture with arrival of data at memory device
    5.
    发明专利
    Method and apparatus for determining actual write latency and accurately aligning start of data capture with arrival of data at memory device 有权
    用于确定实际写入延迟的方法和装置，并精确地按照存储器件上的数据到达数据捕获开始

    公开(公告)号：JP2009104651A

    公开(公告)日：2009-05-14

    申请号：JP2009025395

    申请日：2009-02-05

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー, インク.

    Inventor： BRIAN JOHNSON ,  KEETH BRENT ,  MANNING TROY A

    IPC: G06F12/00 ,  G11C11/407 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

    CPC classification number: G11C29/028 ,  G06F13/1694 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/401 ,  G11C29/50012 ,  G11C2207/2254

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device. SOLUTION: The actual time of arrival of data at the inputs to the memory device is determined by sending back-to-back write commands along with a predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于准确地确定数据在存储器件相对于写时钟的实际到达以精确对准数据捕获的开始和数据到达存储器件的方法和装置。 解决方案：将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。 数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。 然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准存储器件。 版权所有（C）2009，JPO＆INPIT

    Translation layer in solid state storage device
    6.
    发明专利
    Translation layer in solid state storage device 有权
    固态存储设备中的翻译层

    公开(公告)号：JP2014063511A

    公开(公告)日：2014-04-10

    申请号：JP2013239909

    申请日：2013-11-20

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー, インク.

    Inventor： MANNING TROY A

    IPC: G06F3/06 ,  G06F3/08 ,  G06F12/00 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C16/102 ,  Y02B60/1225 ,  Y02D10/13

    Abstract: PROBLEM TO BE SOLVED: To provide solid state storage devices and methods for flash translation layers.SOLUTION: In one translation layer, a sector indication is translated to a memory location by a parallel unit look-up table configured by memory device enumeration at initialization. Each table entry comprises communication channel information, chip enable information, logical unit information and plane information, for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

    Abstract translation: 要解决的问题：提供闪存转换层的固态存储设备和方法。解决方案：在一个转换层中，通过在初始化时由存储器设备枚举配置的并行单元查找表将扇区指示转换为存储器位置。 每个表条目包括针对找到的每个操作存储器件的通信信道信息，芯片使能信息，逻辑单元信息和平面信息。 当接收到扇区指示时，模函数对查找表的条目进行操作，以便确定与扇区指示相关联的存储器位置。

    Memory device and method having data with multiple pre-fetch i/o configuration
    7.
    发明专利
    Memory device and method having data with multiple pre-fetch i/o configuration 审中-公开
    具有多个预充电I / O配置的数据的存储器件和方法

    公开(公告)号：JP2010015685A

    公开(公告)日：2010-01-21

    申请号：JP2009210519

    申请日：2009-09-11

    Applicant: Micron Technology Inc ,  マイクロン テクノロジー, インク.

    Inventor： KEETH BRENT ,  JOHNSON BRAIN ,  MANNING TROY A

    IPC: G11C11/409 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/407

    CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    Abstract: PROBLEM TO BE SOLVED: To provide a memory data bus being operable as either a high-speed narrow data bus or a low speed wide data bus. SOLUTION: In either mode, 32 bits of data from each of two memory arrays are pre-fetched into respective sets of 32 flip-flop 120. In high-speed mode, the pre-fetched data bits are transferred in parallel to four parallel-to-serial converters 150a, which transform the parallel data bits to a burst of eight serial data bits and apply the burst to a respective one of four data bus terminals 160. In the low speed mode, two sets of pre-fetched data bits are transferred in parallel to eight parallel-to serial converters, which transform the parallel data bits to a burst of eight serial data bits and apply the burst to a respective one of eight data bus terminals. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供可操作为高速窄数据总线或低速宽数据总线的存储器数据总线。 解决方案：在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器120的集合中。在高速模式中，预取数据位被并行转移 四个并行到串行转换器150a，其将并行数据位转换为八个串行数据位的脉冲串，并将该脉冲串应用于四个数据总线端子160中的相应一个。在低速模式中，两组预取 数据位并行传输到八个并行到串行转换器，它们将并行数据位转换为八个串行数据位的脉冲串，并将该脉冲串应用于八个数据总线端子中的相应一个。 版权所有（C）2010，JPO＆INPIT

    Method and apparatus for generating internal clock signal that is synchronized to external clock signal
    8.
    发明专利
    Method and apparatus for generating internal clock signal that is synchronized to external clock signal 审中-公开
    用于产生同步到外部时钟信号的内部时钟信号的方法和装置

    公开(公告)号：JP2007151183A

    公开(公告)日：2007-06-14

    申请号：JP2007041506

    申请日：2007-02-21

    Applicant: Micron Technol Inc ,  マイクロン・テクノロジー・インコーポレーテッドMicron Technology,Inc.

    Inventor： MANNING TROY A

    IPC: G11C11/407 ,  H03L7/08 ,  G06F1/10 ,  G06F1/12 ,  H03K5/00 ,  H03K5/13 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099

    CPC classification number: G06F1/10 ,  H03K5/131

    Abstract: PROBLEM TO BE SOLVED: To provide a clock circuit for generating an internal clock signal synchronized to an external clock signal. SOLUTION: A clock generator circuit for an integrated circuit comprised of a phase-locked loop (PLL) includes a phase detector comparing the phase of a delayed external clock signal with the phase of an internal clock signal. An error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to the delay of an external clock signal when it is coupled to the phase detector. The offset error signal is applied to a control input of a voltage controlled oscillator which generates the internal clock signal. The phase of the internal clock signal is thus adjusted so that it may be substantially the same as the phase of the external clock signal. The voltage controlled oscillator is constructed to operate in a plurality of discrete frequency bands so that the offset error signal may need to only control the frequency of the internal clock signal over a relatively small range. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于产生与外部时钟信号同步的内部时钟信号的时钟电路。 解决方案：用于由锁相环（PLL）组成的集成电路的时钟发生器电路包括相位检测器，将延迟的外部时钟信号的相位与内部时钟信号的相位进行比较。 对应于两个时钟信号之间的相位差的误差信号被施加到差分放大器，其中误差信号偏移与外部时钟信号耦合到相位检测器时的延迟相对应的值。 偏移误差信号被施加到产生内部时钟信号的压控振荡器的控制输入端。 因此调整内部时钟信号的相位，使得其可以与外部时钟信号的相位基本相同。 压控振荡器被构造为在多个离散频带中操作，使得偏移误差信号可能仅需要在相对小的范围内控制内部时钟信号的频率。 版权所有（C）2007，JPO＆INPIT

    Method and circuit for producing high-speed count
    9.
    发明专利
    Method and circuit for producing high-speed count 审中-公开
    生产高速计数器的方法和电路

    公开(公告)号：JP2006314134A

    公开(公告)日：2006-11-16

    申请号：JP2006203465

    申请日：2006-07-26

    Applicant: Micron Technol Inc ,  マイクロン・テクノロジー・インコーポレーテッドMicron Technology,Inc.

    Inventor： MANNING TROY A

    IPC: H03K21/00 ,  H03K23/42 ,  H03K23/00 ,  H03K23/44 ,  H03K23/54

    CPC classification number: H03K23/44 ,  H03K23/54

    Abstract: PROBLEM TO BE SOLVED: To provide a high-speed counter circuit which produces digital counts, with a plurality of bits to control the timing of operations in a memory device.
    SOLUTION: A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetric clock signals for driving each of the registers. The registers are formed from input and output stages, each having two sets of switches. The first set of switches in each stage provides a supply voltage to a stage output, in response to the asymmetric clocks. The second set of switches supplies a ground to the stage output, in response to the asymmetric clocks. To accelerate response of the switching circuits, isolation switches decouple the first set of switches in each pair from the stage output during switching of the second set of switches, thereby removing the load of stage output due to the second set of switches.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种产生数字计数的高速计数器电路，具有多个位以控制存储器件中的操作时序。 解决方案：一个计数器电路包括由两个相移时钟驱动的一系列寄存器。 计数器电路中的时钟发生器产生用于驱动每个寄存器的四个非对称时钟信号。 寄存器由输入和输出级形成，每级具有两组开关。 响应于不对称时钟，每个级中的第一组开关为电平输出提供电源电压。 响应于不对称时钟，第二组开关为舞台输出提供接地。 为了加速开关电路的响应，隔离开关在第二组开关切换期间将每对开关中的第一组开关与级输出分离，从而消除由于第二组开关而产生的级输出的负载。 版权所有（C）2007，JPO＆INPIT

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