公开(公告)号：CA1292584C

公开(公告)日：1991-11-26

申请号：CA574720

申请日：1988-08-15

Applicant: MOTOROLA INC

Inventor： LINDER DONALD L ,  GOODE STEVE H ,  KAZECKI HENRY L ,  DENNIS DONALD W ,  BAKER JAMES C

IPC: H04L1/02 ,  H04B7/08

Abstract: CM-00380H ANTENNA SELECTION CONTROL CIRCUIT An antenna switch control circuit for use in achieving antenna selection diversity in TDM RF receivers. RSSI for at least one antenna is monitored during time slots containing information not of interest. This information can then be compared with other antenna performance information to allow a selection to be made such that the receiver generally operates with the antenna receiving the strongest signal. In one embodiment, all possible antennas are monitored during a time slot containing information not of interest. In another embodiment, RSSI for the selected antenna can be monitored during the time slot of interest, such that antenna selection can again be varied should the selected antenna diminish in performance.

公开(公告)号：GB2313752B

公开(公告)日：2000-11-22

申请号：GB9708371

申请日：1997-04-25

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C

IPC: H03H17/00 ,  H03G7/00 ,  H03G11/00 ,  H03M7/50 ,  H04B14/04 ,  H03M7/30

Abstract: A bit-serial digital expandor includes a bit-serial dual scaler block (340), a bit-serial rectifier block (320), a bit-serial lowpass wave digital filter block (350), a bit-serial scaler with overflow detection block (360), a bit-serial multiplier block (380), and a bit-serial scaler and clipper block (395). This bit-serial expandor can be used in an AMPS cellular telephone receiver to produce a receiver having a lower silicon area, gate count, and current drain compared to equivalent parallel architecture receivers.

公开(公告)号：CA2202959C

公开(公告)日：2000-02-15

申请号：CA2202959

申请日：1997-04-17

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  OLIVER JOHN PAUL

IPC: H03G7/00 ,  H03G11/00 ,  H03M7/30

Abstract: A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216)and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

公开(公告)号：CA2102406C

公开(公告)日：1998-11-24

申请号：CA2102406

申请日：1993-01-21

Applicant: MOTOROLA INC

Inventor： LAROSA CHRISTOPHER P ,  BAKER JAMES C ,  CARNEY MICHAEL J

IPC: H04B7/26 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H04L7/027 ,  H04Q7/22 ,  H04Q7/32 ,  H04B1/40

Abstract: The present disclosure includes a discussion of a method of synchronizing a samp ling clock signal to a received data signal (131). The clock recovery circuit (127) generates several clock signals (339 341 , 343, 345) at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clo ck signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuit ry (127) generates error signals (347 349, 351 353) representing the difference between the phase of the received data signal and th e phase of each clock signal. The error signals (347, 349, 351, 353) are processed over multiple symbol times to determine the o ptimal sampling phase. The clock recovery circuit (127) then adjusts or maintains the phase of the symbol clock (139) to provide t he optimal sampling phase.

公开(公告)号：BR9703349A

公开(公告)日：1998-08-04

申请号：BR9703349

申请日：1997-05-30

Applicant: MOTOROLA INC

Inventor： OLIVER JOHN P ,  BAKER JAMES C

IPC: H03G7/00 ,  H03G11/00 ,  H03M7/30 ,  H04Q7/32

Abstract: A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

公开(公告)号：GB2314742A

公开(公告)日：1998-01-07

申请号：GB9710089

申请日：1997-05-20

Applicant: MOTOROLA INC

Inventor： GOODE STEVEN H ,  BAKER JAMES C ,  CARNEY MICHAEL J

IPC: H03D3/00 ,  H04L27/14

Abstract: The digital FM receiver back end receives an analog intermediate frequency signal from a radio frequency front end (310) having a heterodyne circuit (312) and an intermediate frequency filter (314). In the receiver back end (307), a digital demodulator (330) having a hard limiter (333), a direct phase digitizer (336), and a phase differential circuit (339) produces a digital phase differential signal from the analog intermediate frequency signal. Next, a digital processor (360) filters and reduces noise in the digital phase differential signal using a bandpass filter (362), a de-emphasis filter (364), and an expandor (366). Finally, a pulse-width-modulation audio amplifier (380) prepares the signal for reproduction on an audio speaker (390). The digital FM receiver back end avoids inherent DC offset problems common to analog FM receivers, and it also offers a reduced complexity, size, and power consumption alternative to conventional digital FM receivers.

公开(公告)号：CA2054364C

公开(公告)日：1997-02-25

申请号：CA2054364

申请日：1991-10-28

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  KAZECKI HENRY L ,  GOODE STEVEN H

IPC: H04L27/00 ,  H04L27/227 ,  H04L27/22 ,  H03D3/00

Abstract: The .pi./4-QPSK (quadrature phase shifted keying) coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The .pi./4-QPSK coherent detector recovers bursts of data, in a TDMA system, that has been encoded in an amplitude modulated vector's phase angle. The .pi./4-QPSK coherent detector detects the .pi./4QPSK constellation of the incoming modulated signal and outputs the recovered data stream.

公开(公告)号：GB2271492B

公开(公告)日：1996-03-20

申请号：GB9322404

申请日：1993-01-21

Applicant: MOTOROLA INC

Inventor： LAROSA CHRISTOPHER P ,  CARNEY MICHAEL J ,  BAKER JAMES C

IPC: H04B7/26 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H04L7/04

Abstract: The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

公开(公告)号：GB2251161B

公开(公告)日：1995-05-31

申请号：GB9123925

申请日：1991-11-11

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  KAZECKI HENRY L ,  GOODE STEVEN H

IPC: H04L27/00 ,  H04L27/227 ,  H03L7/00 ,  H04L27/38

Abstract: The pi /4-QPSK coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The pi /4-QPSK coherent detector recovers bursts of data, in a TDMA system, that has been encoded in an amplitude modulated vector's phase angle. The pi /4-QPSK coherent detector detects the pi /4-QPSK constellation of the incoming modulated signal and outputs the recovered data stream.

公开(公告)号：CA2054350C

公开(公告)日：1995-04-11

申请号：CA2054350

申请日：1991-10-28

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  CARNEY MICHAEL J

IPC: H03L7/085 ,  H03L7/08

Abstract: The method of the present invention provides fast frequency acquisition in a PLL. The peak voltage for a phase error signal is detected at time tp and a voltage controlled oscillator warp voltage is sampled at tp. The new warp voltage to the voltage controlled oscillator is set to what the warp voltage was at tp. The bandwidth of the loop is then narrowed and the warp voltage is averaged over a number of samples. The warp voltage is then set to the average warp voltage and the loop bandwidth is widened.