公开(公告)号：EP0888675A4

公开(公告)日：2000-08-16

申请号：EP97921090

申请日：1997-04-02

Applicant: MOTOROLA INC

Inventor： O'DEA ROBERT J ,  STENGEL ROBERT E

IPC: H04L27/20 ,  H04L27/36 ,  H04L1/00

CPC classification number: H04L27/2032 ,  H04L27/368

Abstract: A modulated signal, having a varying magnitude signal envelope, is conditioned, such as to facilitate amplification (500). Minimum values are determined values for portions of the signal envelope (520, 530), and a window expansion function applied to scale each portion of the signal envelope having a minimum value below a particular threshold, such that each scaled portion has a new minimum value of at least the particular threshold (535, 540, 550, 555).

公开(公告)号：EP0569486A4

公开(公告)日：1993-09-10

申请号：EP92904869

申请日：1991-12-24

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  DAVENPORT ROGER A

IPC: H04B1/04 ,  H04B7/005 ,  H04B7/26 ,  H04B7/02

CPC classification number: H04W52/146 ,  H04W52/245 ,  H04W52/248

Abstract: The transmit power of a subscriber unit (106) operating in a communication system (100) is adjusted by a value which corresponds to the measured noise characteristic of a received signal at a receiving site (104).

公开(公告)号：BRPI0510077A

公开(公告)日：2007-10-16

申请号：BRPI0510077

申请日：2005-03-14

Applicant: MOTOROLA INC

Inventor： WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO MANUEL P JR ,  GAILUS PAUL H ,  STENGEL ROBERT E

IPC: H03L7/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H03L7/16

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source ( 320 ) for generating a clock signal ( 322 ) having an adjustable frequency; an adjustment and tap selection controller ( 310 ) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line ( 330 ) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit ( 370 ) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

公开(公告)号：CA2582350A1

公开(公告)日：2006-04-13

申请号：CA2582350

申请日：2005-09-14

Applicant: MOTOROLA INC

Inventor： GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: H03L1/00 ,  H03K3/011 ,  H03K5/14 ,  H03L7/06 ,  H03M1/08 ,  H04B15/00

Abstract: A direct digital synthesizer (DDS) ( 300 ) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) ( 317 ). The DDS ( 300 ) includes one or more dither sources ( 307 ) and a random access memory (RAM) ( 305 ). The RAM ( 305 ) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source ( 307 ) to compensate unequal unit delay values in the DTC ( 317 ).

公开(公告)号：CA2250872C

公开(公告)日：2004-06-29

申请号：CA2250872

申请日：1997-04-02

Applicant: MOTOROLA INC

Inventor： O'DEA ROBERT J ,  STENGEL ROBERT E

IPC: H04L27/20 ,  H04L27/36 ,  H04L1/00 ,  H04L27/34

Abstract: A modulated signal, having a varying magnitude signal envelope, is conditioned, such as to facilitate amplification (500). Minimum values are determined values for portions of the signal envelope (520, 530), and a window expansion function applied to scale each portion of the signal envelope having a minimum value below a particular threshold, such that each scaled portion has a new minimum value of at least the particular threshold (535, 540, 550, 555).

公开(公告)号：AU2002362108A1

公开(公告)日：2003-07-24

申请号：AU2002362108

申请日：2002-12-10

Applicant: MOTOROLA INC

Inventor： MARTIN FREDERICK L ,  STENGEL ROBERT E ,  JUAN JUI-KUO

IPC: H03L7/081 ,  H03L7/16 ,  H03L7/22 ,  H04J1/20

Abstract: A digital frequency synthesizer includes one or more reference clocks ( 104, 1316, 1502 A, 1504 A, 1506 A) optionally coupled through one or more pulse width reducers ( 106 ) to one or more main delay lines ( 108, 702, 1502 B, 1504 B, 1506 B) that include a plurality of output taps ( 108 B- 108 I, 702 B- 702 E). During at least certain periods of the reference clock ( 104 ) a plurality of the output taps are coupled to a common output ( 130, 1312, 1508 ), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates ( 114, 128, 720-724, 1420-1434 ) that are switched by gating pulses that are received from decoders ( 148, 150, 1418 ) via gating signal delay lines ( 134-146, 704-718, 1404-1416 ).

公开(公告)号：AU2879302A

公开(公告)日：2002-06-18

申请号：AU2879302

申请日：2001-12-07

Applicant: MOTOROLA INC

Inventor： PERKINS MATTHEW R ,  STENGEL ROBERT E ,  ALLEN VERNON A

IPC: H04B10/10 ,  H04B10/00

Abstract: An interference-robust coded-modulation scheme for optical communications and a method for modulating illumination for optical communications include optical signal transmitters connected to signal multipliers. The signal to be transmitted is multiplied by a pseudo-random noise code and transmitted within the transmitter emissions. A receiver converts the received modulated light and correlates the received signal. An estimate of the signal to be transmitted is made by multiplying the received signal by the noise code and correlating such multiplication over the length of the code. A threshold switch outputs the correlation result to a bit estimator approximately when a deterministic peak of the output signal exceeds a threshold.

公开(公告)号：AU7276998A

公开(公告)日：1998-11-27

申请号：AU7276998

申请日：1998-04-30

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  OLSON SCOTT A

IPC: H03F3/68 ,  H03F1/02 ,  H03F3/60 ,  H04B1/04

Abstract: An apparatus (100) uses power recovery from a combining circuit (125) to improve efficiency. A power combiner (125) generates multiple output signals (127, 133) from a combination of input signals (113, 114). One of the output signals from the power combiner is coupled to a power recovery circuit (135), and energy is recovered and preferably stored for later use.

公开(公告)号：GB2320381A

公开(公告)日：1998-06-17

申请号：GB9723473

申请日：1997-11-07

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  OLSON SCOTT A

IPC: H03F1/02 ,  H03F1/32 ,  H04L27/36

Abstract: An arrangement for reducing the distortion in a power amplifier arrangement 230,240 for a transmitter in which the power of in-phase and quadrature components are sensed 272,274 as well as the total power after the components are summed 276. These results are used in controlling baseband pre-distortion and the amplifiers 230 and 240. A training sequence may also be used.

公开(公告)号：CA2250872A1

公开(公告)日：1997-10-16

申请号：CA2250872

申请日：1997-04-02

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  O'DEA ROBERT J

IPC: H04L27/20 ,  H04L27/36 ,  H04L1/00 ,  H04L27/34

Abstract: A modulated signal, having a varying magnitude signal envelope, is conditioned, such as to facilitate amplification (500). Minimum values are determined values for portions of the signal envelope (520, 530), and a window expansion function applied to scale each portion of the signal envelope having a minimum value below a particular threshold, such that each scaled portion has a new minimum value of at least the particular threshold (535, 540, 550, 555).