-
公开(公告)号：AU2002362108A1
公开(公告)日：2003-07-24
申请号：AU2002362108
申请日：2002-12-10
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L , STENGEL ROBERT E , JUAN JUI-KUO
Abstract: A digital frequency synthesizer includes one or more reference clocks ( 104, 1316, 1502 A, 1504 A, 1506 A) optionally coupled through one or more pulse width reducers ( 106 ) to one or more main delay lines ( 108, 702, 1502 B, 1504 B, 1506 B) that include a plurality of output taps ( 108 B- 108 I, 702 B- 702 E). During at least certain periods of the reference clock ( 104 ) a plurality of the output taps are coupled to a common output ( 130, 1312, 1508 ), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates ( 114, 128, 720-724, 1420-1434 ) that are switched by gating pulses that are received from decoders ( 148, 150, 1418 ) via gating signal delay lines ( 134-146, 704-718, 1404-1416 ).
-
公开(公告)号：AT349809T
公开(公告)日：2007-01-15
申请号：AT02773869
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
-
公开(公告)号：AU2002337964A1
公开(公告)日：2003-05-19
申请号：AU2002337964
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： STENGEL ROBERT E , JUAN JUI-KUO , BOCKELMAN DAVID E , MARTIN FREDERICK L
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
-
Patent Agency Ranking
公开(公告)号：DE60217164T2
公开(公告)日：2007-10-31
申请号：DE60217164
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL E , MARTIN L , BOCKELMAN E
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
-
公开(公告)号：DE60217164D1
公开(公告)日：2007-02-08
申请号：DE60217164
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL E , MARTIN L , BOCKELMAN E
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
-
公开(公告)号：HK1069025A1
公开(公告)日：2005-05-06
申请号：HK05101153
申请日：2005-02-12
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
IPC: H03L20060101 , H03H20060101 , H03L7/07 , H03L7/081 , H03L7/14 , H03L7/16
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
-
公开(公告)号：WO03041276A3
公开(公告)日：2003-07-10
申请号：PCT/US0233935
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
CPC classification number: H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
Abstract translation: 在若干实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个次级延迟元件（162,164,270,310）。 在一个实施例中，使用主延迟线（24）粗略地选择频率输出，同时使用无源或有源二次延迟元件（162,164,270,310）来增加主延迟线的分辨率（ 24）。 在被动实施例中，通过从主延迟线（24）的输出抽头选择分量作为用于无源次级延迟元件（310）的驱动信号来提供粗调和选择输出 来自二级延迟元件（310）以提供精选。
-
公开(公告)号：EP1444783A4
公开(公告)日：2005-02-02
申请号：EP02773869
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
CPC classification number: H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.02 seconds)
