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公开(公告)号：WO03005622A2
公开(公告)日：2003-01-16
申请号：PCT/US0220853
申请日：2002-07-02
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L , STENGEL ROBERT E , BAUTISTA EDWIN E
CPC classification number: H04L27/2007
Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).
Abstract translation: 提供了相移键调制器（100,500,1000,1400,1700），其中使用多相信号源（108,1402,1406-1412,1702）来产生载波信号的多个相位。 选择器（110）用于选择载波信号的相位或序列，以表示从二进制数据源（102,1422）接收的每个位模式。 多相信号源优选地包括多相振荡器，其包括可变传播延迟反相器（202）的锁相环。 优选地，相位序列器（502）用于选择相位的单调序列以表示每个位模式。 优选地，两个相位选择器（110,1004）用于同时选择载波信号的两相，并且相位内插器（1106）用于从由两个相位选择器（110,1004）选择的两相中产生相位序列， 。
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公开(公告)号：HK1069025A1
公开(公告)日：2005-05-06
申请号：HK05101153
申请日：2005-02-12
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
IPC: H03L20060101 , H03H20060101 , H03L7/07 , H03L7/081 , H03L7/14 , H03L7/16
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
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公开(公告)号：AT126411T
公开(公告)日：1995-08-15
申请号：AT90907725
申请日：1990-05-17
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L
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公开(公告)号：AU2002362108A1
公开(公告)日：2003-07-24
申请号：AU2002362108
申请日：2002-12-10
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L , STENGEL ROBERT E , JUAN JUI-KUO
Abstract: A digital frequency synthesizer includes one or more reference clocks ( 104, 1316, 1502 A, 1504 A, 1506 A) optionally coupled through one or more pulse width reducers ( 106 ) to one or more main delay lines ( 108, 702, 1502 B, 1504 B, 1506 B) that include a plurality of output taps ( 108 B- 108 I, 702 B- 702 E). During at least certain periods of the reference clock ( 104 ) a plurality of the output taps are coupled to a common output ( 130, 1312, 1508 ), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates ( 114, 128, 720-724, 1420-1434 ) that are switched by gating pulses that are received from decoders ( 148, 150, 1418 ) via gating signal delay lines ( 134-146, 704-718, 1404-1416 ).
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公开(公告)号：BR9610115A
公开(公告)日：1999-02-23
申请号：BR9610115
申请日：1996-08-21
Applicant: MOTOROLA INC
Inventor： CARRALERO CESAR W , MARTIN FREDERICK L
Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).
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Patent Agency Ranking
公开(公告)号：DE19681546T1
公开(公告)日：1998-08-20
申请号：DE19681546
申请日：1996-08-21
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L , CARRALERO CESAR W
Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).
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公开(公告)号：IE61813B1
公开(公告)日：1994-11-30
申请号：IE203990
申请日：1990-06-07
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L
Abstract: A phase detector is provided for detecting the phase difference between a first input signal and a second input signal and providing an output corresponding thereto. The phase detector comprises a dual state phase detector, a tri-state phase detector, a control input for receiving a control signal, and a control circuit for selecting either the dual state phase detector or tri-state phase detector. The dual state phase detector compares the phase difference between the first input signal and the second input signal. The tri-state phase detector compares the phase difference between the second input signal and the inverse of the first input signal. The control circuit selects the output of the dual state phase detector or selects the output of the tri-state phase detector based upon the control signal.
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公开(公告)号：NZ234592A
公开(公告)日：1992-11-25
申请号：NZ23459290
申请日：1990-07-20
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L
Abstract: A phase detector is provided for detecting the phase difference between a first input signal and a second input signal and providing an output corresponding thereto. The phase detector comprises a dual state phase detector, a tri-state phase detector, a control input for receiving a control signal, and a control circuit for selecting either the dual state phase detector or tri-state phase detector. The dual state phase detector compares the phase difference between the first input signal and the second input signal. The tri-state phase detector compares the phase difference between the second input signal and the inverse of the first input signal. The control circuit selects the output of the dual state phase detector or selects the output of the tri-state phase detector based upon the control signal.
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公开(公告)号：AT349809T
公开(公告)日：2007-01-15
申请号：AT02773869
申请日：2002-10-23
Applicant: MOTOROLA INC
Inventor： JUAN JUI-KUO , STENGEL ROBERT E , MARTIN FREDERICK L , BOCKELMAN DAVID E
Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.
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公开(公告)号：MY105938A
公开(公告)日：1995-02-28
申请号：MYPI19901226
申请日：1990-07-24
Applicant: MOTOROLA INC
Inventor： MARTIN FREDERICK L
Abstract: A PHASE DETECTOR (20) IS PROVIDED FOR DETECTING THE PHASE DIFFERENCE BETWEEN A FIRST INPUT SIGNAL AND A SECOND INPUT SIGNAL AND PROVIDING AN OUTPUT CORRESPONDING THERETO. THE PHASE DETECTOR COMPRISES A DUAL STATE PHASE DETECTOR (28) . A TRI-STATE PHASE DETECTOR (32), A CONTROL INPUT (2) FOR RECEIVING A CONTROL SIGNAL AND A CONTROL CIRCUIT FOR SELECTING EITHER THE DUAL STATE PHASE DETECTOR (28) OR TRI-STATE PHASE DETECTOR (32). THE DUAL STATE PHASE DETECTOR (28) COMPARES THE PHASE DIFFERENCE BETWEEN THE FIRST INPUT SIGNAL AND THE SECOND INPUT SIGNAL. THE TRI-STATE PHASE DETECTOR (32) COMPARES THE PHASE DIFFERENCE BETWEEN THE SECOND INPUT SIGNAL AND THE INVERSE OF THE FIRST INPUT SIGNAL. THE CONTROL CIRCUIT SELECTS THE OUTPUT OF THE DUAL STATE PHASE DETECTOR (28) OR SELECTS THE OUTPUT OF THE TRI- STATE PHASE DETECTOR (32) BASED UPON THE CONTROL SIGNAL.@@@(FIG. 2)
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